Renesas Hitachi H8S/2191, Hardware Manual

Page: 558 / 1065

Rev. 2.0, 11/00, page 531 of 1037
25.2.5 I
2
C Bus Control Register (ICCR)
7
ICE
0
R/W
6
IEIC
0
R/W
5
MST
0
R/W
4
TRS
0
R/W
3
ACKE
0
R/W
0
SCP
1
W
2
BBSY
0
R/W
1
IRIC
0
R/(W)
*
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
ICCR is an 8-bit readable/writable register that enables or disables the I
2
C bus interface, enables
or disables interrupts, selects master or slave mode and transmission or reception, enables or
disables acknowledgement, confirms the I
2
C bus interface bus status, issues start/stop conditions,
and performs interrupt flag confirmation.
ICCR is initialized to H'01 by a reset.
Bit 7: I
2
C Bus Interface Enable (ICE)
Selects whether or not the I
2
C bus interface is to be used. When ICE is set to 1, port pins
function as SCL and SDA input/output pins and transfer operations are enabled. When ICE is
cleared to 0, the I
2
C bus interface module is disabled, and the internal state is initialized.
The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers
can be accessed when ICE is 1.
Bit 7
ICE Description
0 I
2
C bus interface module disabled, with SCL and SDA signal pins set to port function
SAR and SARX can be accessed. The internal state of the I
2
C bus interface module
is initialized. (Initial value)
1 I
2
C bus interface module enabled for transfer operations (pins SCL and SCA are
driving the bus)
ICMR and ICDR can be accessed
Bit 6: I
2
C Bus Interface Interrupt Enable (IEIC)
Enables or disables interrupts from the I
2
C bus interface to the CPU.
Bit 6
IEIC Description
0 Interrupts disabled (Initial value)
1 Interrupts enabled