Renesas Hitachi H8S/2191, Hardware Manual

Page: 983 / 1065

Rev. 2.0, 11/00, page 956 of 1037
H'D0E2: Serial Control Register 2 SCR2: 32-Byte Buffer SCI2
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5 6 7
R/W R/W
GAP1
0
R/W
ABTIE
R/W
TEIE GAP0 CKS2 CKS1 CKS0
0 1
Transfer data interval select bits
GAP1 GAP0 Transfer data interval
0 0 No interval
0 1 8-clock interval
1 0 24-clock interval
0 1 56-clock interval
Transfer end interrupt enable bit
0 Transfer-end interrupt request is disabled
1 Transfer-end interrupt request is enabled
Transfer interrupt enable bit
0 Transfer interrupt request is disabled
1 Transfer interrupt request is enabled
Bit :
Initial value :
R/W :
Transfer clock select bits
CKS2 CKS1 CKS0 SCK2 pin Clock source Transfer clock frequency
φ
= 10 MHz
φ
= 5 MHz
0 0 0 Sprescaler S
φ
/256 25.6
µ
s 51.2
µ
s
0 0 0
φ
/64 6.4
µ
s 12.8
µ
s
0 0 0
φ
/32 3.2
µ
s 6.4
µ
s
0 0 0
φ
/16 1.6
µ
s 3.2
µ
s
0 0 0
φ
/8 0.8
µ
s 1.6
µ
s
0 0 0
φ
/4 0.4
µ
s 0.8
µ
s
0 0 0
φ
/2
—
0.4
µ
s
0 0 0 External clock
— — —
Prescaler frequency
division rate
SCK2
output
SCK2
input
—
—