Renesas Hitachi H8S/2191, Hardware Manual

Page: 407 / 1065

Rev. 2.0, 11/00, page 380 of 1037
Even when the ICRC or ICRD is used as the buffer register, the input capture flag will be set up
corresponding to the designated edge change of respective input capture signals.
For example, when using the ICRC as the buffer register for the ICRA, when an edge change
having been designated by the IEDGC bit is detected with the input capture signals C and if the
ICIEC bit is duly set, an interrupt request will be issued.
However, in this case, the FRC value will not be transferred to the ICRC.
17.3.6 Input Capture Flag (ICFA through ICFD) Setting Up Timing
The input capture signal works to set the ICFA through ICFD to "1" and, simultaneously, the
FRC value is transferred to the corresponding ICRA through ICRD. Figure 17.9 shows the
timing chart for the above.
Input capture
signal
ICFA to ICFD
ICRA to ICRD
FRC
N
N
Figure 17.9 ICFA through ICFD Setting Up Timing