Renesas Hitachi H8S/2191, Hardware Manual

Page: 661 / 1065

Rev. 2.0, 11/00, page 634 of 1037
(5) Reference Period Mode Register 2 (RFM2)
0
0
1
1
2
1
3
1
4
1
5 6 7
— — — — — — (TBC)
— — — — — —
(R/W)
*
FDS
1 1 1
R/W
Bit :
Initial value :
R/W :
Note:
*
Writable only in the H8S/2194C Series.
RFM2 is an 8-bit read/write register which determines the operational state of the reference
signal generators. Bits 7 to 1 are reserved. If a read is attempted, an undetermined value is read
out.
It is initialized to H'FE by a reset, stand-by or module stop. RFM2 is a byte access-only register;
if accessed by a word, no operation is assured.
Bits 7: TBC Selection Bit (TBC)
Selects whether the reference signals are generated by VD or in free-run in PB mode.
Bit 7
TBC Description
0 Reference signals are generated by VD (This function is effective only in the
H8S/2194C series)
1 Reference signals are generated in free-run (Initial value)
Bits 6 to 1: Reserved
No write is valid. If a read is attempted, an undetermined value is read out.
Bit 0: Field Selection Bit (FDS)
Determines whether selection between ODD or EVEN is made for the field signals when PB
mode was switched over to REC mode, or these signals are synchronized with VD signals within
phase error of 90
°
immediately after the switching over.
Bit 0
FDS Description
0 Generated by the VD signal of ODD or EVEN selected (Initial value)
1 Generated by the VD signal within mode transition phase error of 90
°