Renesas Hitachi H8S/2191, Hardware Manual

Page: 711 / 1065

Rev. 2.0, 11/00, page 684 of 1037
28.6.4 Register Descriptions
(1) Specified DFG Speed Preset Data Register (DFPR)
0
W
13
0
W
14
0
W
15 1 0 3 2 5 4 7
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
W W W W W W W
12
0 0 0 0 0 0
Bit :
Initial value :
R/W :
The specified DFG speed preset data is set in DFPR. When the data is written, a 16-bit preset
data is sent to the preset circuit. The preset data is referenced to H'8000*, and can be calculated
from the following equation.
φ
s/n
Specified DFG speed preset data =H'8000
−
(
−
2)
DFG frequency
φ
s: Servo clock frequency (fosc/2) in Hz
DFG frequency: In Hz
The constant 2 is the presetting interval (see Figure 28.28).
φ
s/n Clock source of selected counter
DFPR is a 16-bit write-only register, and is accessible by word access only. Byte access gives
unassured results. Reads are disabled. DFPR is initialized to H'0000 by a reset, and in standby
mode and module stop mode.
Note: * The preset data value is calculated so that the counter will reach H'8000 when the
error is zero. When the counter value is latched as error data in the DFG speed error
data register (DFER), however, it is converted to a value referenced to H'0000.