Renesas Hitachi H8S/2191, Hardware Manual

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Rev. 2.0, 11/00, page 794 of 1037
Bit 0: DFG Edge Selection Bit (DRF)
Selects the edge of the NCDFG signal used in the drum speed error detector.
Bit 0
DRF Description
0 Selects the rising edge of NCDFG signal (Initial value)
1 Selects the falling edge of NCDFG signal
(3) Description of Operation
The DFG noise removal circuits generates a signal (NCDFG signal) with a delay circuit as a
result of removing noise (signal fluctuation smaller than 2
φ
) from the DFG signal. The
resulted NCDFG signal is behind the time when the DFG signal was detected by 2
φ
. Figure
28.71 shows the NCDFG signal.
DFG
NCDFG
Noise
2 2 2
= fosc
Figure 28.71 NCDFG signal