Renesas Hitachi H8S/2191, Hardware Manual

Page: 353 / 1065

Rev. 2.0, 11/00, page 326 of 1037
15.2.2 Linear Time Counter (LTC)
0
0
1
0
R
2
0
3
0
4 5 6
0
7
R R R R
LTC6
0
R
LTC5
0
R
LTC4
0
R
LTC7 LTC3 LTC2 LTC1 LTC0
Bit :
Initial value :
R/W :
The linear time counter (LTC) is a readable 8-bit up/down-counter. The inputting clock can be
selected by the LMR2 to LMR0 bits of the LMR.
When reset, the LTC is initialized to H'00.
15.2.3 Reload/Compare Match Register (RCR)
0
0
1
0
W
2
0
3
0
4 5 6
0
7
W W W W
RCR6
0
W
RCR5
0
W
RCR4
0
W
RCR7 RCR3 RCR2 RCR1 RCR0
Bit :
Initial value :
R/W :
The reload/compare match register (RCR) is an 8-bit write only register.
When the Timer L is being controlled to the up-counting function, when a compare match value
is set to the RCR, the LTC will be cleared at the same time and the LTC will then start counting
up from the initial value (H'00).
While, when the Timer L is being controlled to the down-counting function, when a reloading
value is set to the RCR, the same value will be loaded to the LTC at the same time and the LTC
will then start counting up from said value. Also, when the LTC underflows, the value of the
RCR will be reloaded to the LTC.
When reset, the RCR is initialized to H'00.