Renesas Hitachi H8S/2191, Hardware Manual

Page: 540 / 1065

Rev. 2.0, 11/00, page 513 of 1037
(3) Receive Operations
Receive operations are performed as described below:
(1) Set PMR25 and PMR27 of PMR2 to 1 and set them to the SI2 and SCK2 pins,
respectively. Set them to the
&6 pin, using PMR30 of PMR3 as necessary.
(2) Set the transfer clock and transfer data intervals (only when an internal clock is in
operation) by setting SCR2.
(3) Set STAR to 5 low-order bits at the receive starting address and EDAR to 5 low-order
bits at the receive ending address. This enables to determine the area in the serial data
buffer where receive data is stored.
(4) Set STF to 1. When PMR30 of PMR3 is set to 0, reception is started by setting STF.
While PMR30 of PMR3 is set to 1, reception is started when low level of the
&6 pin is
detected.
(5) After completion of reception, TEI of SCSR2 is set to 1. STF is cleared to 0.
(6) Read the receive data stored from the serial data buffer.
When an internal clock is selected, synchronous clock is output from the SCK2 pin at the time of
starting reception. When reception has been completed, synchronous clock is not output until
the next STF is set.
When an external clock is selected, data is received, synchronized with the clock input from the
SCK2 pin. If the synchronous clock is continuously input after completion of reception, no
reception is performed as the overrun state has been found and then ORER of the SCSR2 is set
to 1. However, if the
&6 of PMR3 is set to 1, overrun is not detected when the &6 pin is at a
high level.
Data buffer cannot be read or written from CPU during reception or in the
&6 standby mode.
When a Read instruction has been executed, H'FF is read. Even if a Write instruction is
executed, buffer does not change. When a Read/Write instruction has been executed during
reception or in the
&6 input standby mode, WT of the SCSR2 is set.
While
&6 of PMR3 is set to 1, transmission is immediately cut off when a high level of the &6
pin has been detected during transmission, and ABT is set to 1, and then STF is cleared to 0.
The SCK2 and SO2 pins enter the high impedance state. Therefore, note that transmission may
not be carried out while ABT is set to 1, and thus transmission must be resumed after clearing to
0.