Renesas Hitachi H8S/2191, Hardware Manual

Page: 533 / 1065

Rev. 2.0, 11/00, page 506 of 1037
Bit 3: Overrun Error Flag (ORER)
The ORER indicates an occurrence of overrun error while an external clock is used. When
excessive pulses are overlapped with the normal transfer clock caused by external noise, etc.
during transmission, this bit is set to 1. At this time data transfer cannot be assured. When a
clock is input after completion of transmission, it is also found to be in the state of overrun and
this bit is set to 1. However, overrun is not detected when the
&6 pin is at a high level.
Bit 3
ORER Description
0 [Clearing condition] (Initial value)
When 0 is written after reading 1
1 [Setting condition]
When excessive pulses are overlapped with a normal transfer clock while an
external clock is used, or when a clock is input after completion of transmission
Bit 2: Wait Flag (WT)
The WT indicates that read/ or write to serial data buffer (32 bytes) has been executed during
transmission and in the
&6 input standby mode. The instruction at that time is ignored and this
bit is set to 1.
Bit 2
WT Description
0 [Clearing condition] (Initial value)
When 0 is written after reading 1
1 [Setting condition]
When an instruction to read/write to serial data buffer (32 bits) is directed during
transmission and in the
&6
input standby mode
Bit 1: Abort Flag (ABT)
The ABT indicates that the
&6 pin has entered a high level during transmission. When a high
level of the
&6 pin is detected during transfer, the transfer is immediately cut off, and this bit is
set to 1, and then the SCK2 and SO2 pins go into the high impedance state. At this time values
of internal registers other than SCSR2 and serial data buffer (32 bytes) are retained. Transfer
cannot be carried out while this bit is set to 0. Resume transfer after clearing to 0.
Bit 1
ABT Description
0 [Clearing condition] (Initial value)
When 0 is written after reading 1
1 [Setting condition]
During transfer and when
&6
pin has entered a high level