Renesas Hitachi H8S/2191, Hardware Manual, Page: 816 / 1065

Rev. 2.0, 11/00, page 789 of 1037
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DVCFG mask period register (CTMR)
0
1
1
1
W
2
1
W
3 4
1
W
5
1
6 7
— —
— —
W W
CPM5 CPM4
1
W
CPM3 CPM2 CPM1 CPM0
1 1
Bit :
Initial value :
R/W :
The DVCFG mask period register (CTMR) is an 8-bit write-only register. If a read is
attempted, an undetermined value is read out. CTMR is a reload register for the mask
timer (down counter). Set in it the mask period of CFG. The mask period is determined
by the clock specified by bits 1 and 0 of CDVC and the set value (N-1). If data is written
in CTMR, it is written also in the mask timer at the same time.
It is initialized to H'FF by a reset, stand-by or module stop.
Mask period = N
×
clock cycle
(3) Operation
•
Frequency divider
The CFG pulses output from the capstan motor are sent to internal circuitry as the CFG
signal via the zero-cross type comparator. The CFG signal, shaped into a rectangular
waveform by a reshaping circuit, is divided by the CFG frequency dividers, and used in
servo control. The rising edge or both edges of the CFG signal can be selected for the
frequency divider.
The CFG frequency dividers comprises a 7-bit frequency divider with a mask timer for
capstan speed control (DVCFG signal generator) and a 7-bit frequency divider for capstan
phase control (DVCFG2 signal generator).
The DVCFG signal generator consists of a 7-bit reload register (CFG frequency division
register1: CDIVR1), a 7-bit down-counter, and a 6-bit mask timer (with settable mask
interval). Frequency division is performed by setting the frequency-division value in 7-
bit CDIVR1. When the frequency-division value is written in CDIVR1, it is also written
in the down-counter. After frequency division of a CFG signal for which the edge has
been selected, the signal is sent via the mask timer to the capstan speed error detector as
the DVCFG signal.
The DVCFG2 signal generator consists of a 7-bit reload register (CFG frequency division
register 2: CDIVR2) and a 7-bit down-counter. The 7-bit frequency divider does not have
a mask timer. Frequency division is performed by setting the frequency-division value in
CDIVR2. When the frequency-division value is written in CDIVR2, it is also written in
the down-counter. After frequency division of a CFG signal for which the edge has been
selected, the signal is sent to the capstan speed error detector and the Timer L as the
DVCFG2 signal. Frequency division starts when the frequency-division value is written.