Renesas Hitachi H8S/2191, Hardware Manual

Page: 559 / 1065

Rev. 2.0, 11/00, page 532 of 1037
Bit 5: Master/Slave Select (MST)
Bit 4: Transmit/Receive Select (TRS)
MST selects whether the I
2
C bus interface operates in master mode or slave mode.
TRS selects whether the I
2
C bus interface operates in transmit mode or receive mode.
In master mode with the I
2
C bus format, when arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode. In slave receive mode with the addressing
format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according
to the R/W bit in the first frame after a start condition.
Modification of the TRS bit during transfer is deferred until transfer of the frame containing the
acknowledge bit is completed, and the changeover is made after completion of the transfer.
MST and TRS select the operating mode as follows.
Bit 5 Bit 4
MST TRS Description
0 Slave receive mode (Initial value) 0
1 Slave transmit mode
0 Master receive mode 1
1 Master transmit mode
Bit 5
MST Description
0 Slave mode (Initial value)
[Clearing conditions]
(1) When 0 is written by software
(2) When bus arbitration is lost after transmission is started in I
2
C bus format master
mode
1 Master mode
[Setting conditions]
(1) When 1 is written by software (in cases other than clearing condition 2)
(2) When 1 is written in MST after reading MST = 0 (in case of clearing condition 2)