Rev. 2.0, 11/00, page 86 of 1037
4.10
Direct Transition
4.10.1
Overview of Direct Transition
There are three operating modes in which the CPU executes programs:
high-speed
mode, medium-speed mode, and subactive mode. A transition between high-speed mode and
subactive mode without halting the program* is called a direct transition. A direct transition can
be carried out by setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction.
After the transition, direct transition interrupt exception handling is started.
(1) Direct Transition from High-Speed Mode to Subactive Mode
If a SLEEP instruction is executed in high-speed mode while the SSBY bit in SBYCR, the
LSON bit and DTON bit in LPWRCR, and the TMA3 bit in TMA (Timer A) are all set to 1,
a transition is made to subactive mode.
(2) Direct Transition from Subactive Mode to High-Speed Mode/Medium-Speed Mode
If a SLEEP instruction is executed in subactive mode while the SSBY bit in SBYCR is set to
1, the LSON bit is cleared to 0 and the DTON bit is set to 1 in LPWRCR, and the TMA3 bit
in TMA (Timer A) is set to 1, after the elapse of the time set in bits STS2 to STS0 in
SBYCR, a transition is made to directly to high-speed mode.
Note: *
At the time of transition from subactive mode to high- or medium-speed mode, an
oscillation stabilization wait time is generated.
Summary of Contents for Hitachi H8S/2191
Page 123: ...Rev 2 0 11 00 page 96 of 1037...
Page 149: ...Rev 2 0 11 00 page 122 of 1037...
Page 197: ...Rev 2 0 11 00 page 170 of 1037...
Page 247: ...Rev 2 0 11 00 page 220 of 1037...
Page 249: ...Rev 2 0 11 00 page 222 of 1037...
Page 347: ...Rev 2 0 11 00 page 320 of 1037...
Page 357: ...Rev 2 0 11 00 page 330 of 1037...
Page 417: ...Rev 2 0 11 00 page 390 of 1037...
Page 431: ...Rev 2 0 11 00 page 404 of 1037...
Page 439: ...Rev 2 0 11 00 page 412 of 1037...
Page 457: ...Rev 2 0 11 00 page 430 of 1037...
Page 525: ...Rev 2 0 11 00 page 498 of 1037...
Page 543: ...Rev 2 0 11 00 page 516 of 1037...
Page 845: ...Rev 2 0 11 00 page 818 of 1037...