Renesas Hitachi H8S/2191, Hardware Manual, Page: 956 / 1065

Rev. 2.0, 11/00, page 929 of 1037
H'D059: Capstan Phase Error Detection Control Register
CPGCR: Capstan Error Detector
0
1
1 2
1
3
0
4
0
R/W
5
0
6
0
7
R/W R/(W)
*
CPOVF
R/W
CPCS0
0
R/W
CPCS1 CR/RF SELCFG2
1
Note: * Only 0 can be written.
Preset signal select bit
0 Preset by REF30P signal
1 Preset by CRRF signal
Preset, latch signal select bit
0 Preset by CAPREF30 signal and latch by DVCTL signal
1 Preset by REF30P signal and latch by DVCFG2 signal
Bit :
Initial value :
R/W :
Clock source select bit
CPCS1 CPCS0
0 0
φ
s
1
φ
s/2
1 0
φ
s/4
1
φ
s/8
Counter overflow flag
0 Normal status
1 Counter overflows.
Description
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H'D05A: Specified Capstan Phase Preset Data Register 2 CPPR2: Capstan Error Detector
0
W
13
0
W
14
0
W
15 1 0 3 2 5 4 7
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
W W W W W W W
12
0 0 0 0 0 0
Bit :
Initial value :
R/W :
H'D05C: Specified Capstan Phase Preset Data Register 1 CPPR1: Capstan Error Detector
0
0
1
0
W
2
0
W
3
0
4
1
5
1
6
1
7
W W
1
Bit :
Initial value :
R/W :
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