Renesas Hitachi H8S/2191, Hardware Manual, Page: 758 / 1065

Rev. 2.0, 11/00, page 731 of 1037
Bit 4: Drum Phase System Z
-1
Initialization Bit (DZPON)
Reflects the DZp value on Z
-1
of the phase system when computation processing of the drum
phase system begins. If 1 was written, it is reflected on the computation, and then cleared to 0.
Set this bit after writing data to DZp.
Bit 4
DZPON Description
0 DZp value is not reflected on Z
-1
of the phase system (Initial value)
1 DZp value is reflected on Z
-1
of the phase system
Bit 3: Drum Speed System Z
-1
Initialization Bit (DZSON)
Reflects the DZs value on Z
-1
of the speed system when computation processing of the drum
speed system begins. If 1 was written, it is reflected on the computation, and then cleared to 0.
Set this bit after writing data to DZs.
Bit 3
DZSON Description
0 DZs value is not reflected on Z
-1
of the speed system (Initial value)
1 DZs value is reflected on Z
-1
of the speed system
Bits 2 to 0: Drum System Output Gain Control Bits (DSG2, DSG1, DSG0)
Control the gain output to DRMPWM.
Bit 2 Bit 1 Bit 0
DSG2 DSG1 DSG0 Description
0
×
1 (Initial value) 0
1
×
2
0
×
4
0
1
1
×
8
0
×
16 0
1 (
×
32)
*
0 (
×
64)
*
1
1
1 Invalid (Do not set)
Note:
*
Setting optional