Renesas Hitachi H8S/2191, Hardware Manual

Page: 818 / 1065

Rev. 2.0, 11/00, page 791 of 1037
•
Mask timer
The capstan mask timer is a 6-bit reload timer that uses a prescaled clock as a clock
source.
The mask timer is used for masking the DVCFG signal intended for controlling the
capstan speeds.
The capstan mask timer prevents edge detection to be carried out for an unnecessarily
long duration by masking the edge detection for a certain period. The above trouble can
result from abnormal revolution (runout) of the capstan motor because its revolution has
to cover a wide range speeds from the slow/still up to the high speed search.
The capstan mask timer is started by output of a pulse edge in the divided CFG signal
(DVCFG). While the timer is running, a mask signal disables the output of further
DVCFG pulses. The mask signal is shown in Figure 28.67.
The mask timer status can be recognized by reading the CMK flag in the DVCFG control
register (CDVC).
Mask
DVCFG
Mask timer
underflow
Figure 28.67 Mask Signal