Renesas Hitachi H8S/2191, Hardware Manual

Page: 735 / 1065

Rev. 2.0, 11/00, page 708 of 1037
Bits 1 and 0: Capstan Lock Counter Setting Bits (CFRCS1, CFRCS0)
Sets the number of times where drum lock has been determined (DVCFG has been detected in
the range set by the lock range data register). It sets the capstan lock flag if it detected the set
number of times of occurrence of capstan lock. If a DVCFG signal is detected outside the lock
range after data is written in CFRCS1 and CFRCS0, data is stored in the lock counter.
Note: If CFRCS1 or CFRCS0 is read-accessed, the counter value is read out. If bit 3 (capstan
lock flag) is 1 and the capstan lock counter's value is 3, it indicates that the capstan
speed system is locked. The capstan look counter stops until lock is released after
underflow.
Bit 1 Bit 0
CFRCS1 CFRCS0 Description
0 Underflow after lock was detected once (Initial value) 0
1 Underflow after lock was detected twice
0 Underflow after lock was detected three times 1
1 Underflow after lock was detected four times
28.8.5 Description of Operation
The capstan speed error detector detects the speed error based on the reference value set in the
CFG speed preset register (CFPR). The reference value set in CFPR is preset in the counter by
the DVCFG signal, and counts down by the selected clock. The timing of the counter presetting
and the error data latching can be selected between the rising or falling edge of the DVCFG
signal. See section 28.14.3, CFG Frequency Divider. The error data detected is sent to the
digital filter circuit. The error data is signed binaries. It takes a positive number (+) if the speed
is slower than the specified speed, a negative number (-) if the speed is faster, or 0 if it had no
error (revolving at the specified speed). Figure 28.33 shows an example of operation to detect
the capstan speed.
(a) Setting the error data limit
A limit can be set to the error data sent to the digital filter circuit using the CFG lock data
register (CFRUDR, CFRLDR). Set the upper limit of the error data in CFRUDR and the
lower limit in CFRLDR, and write 1 in the CFRFON bit. If the error data is beyond the limit
range, the CFRLDR value is sent if a negative number is latched, or the CFRUDR value is
sent if a positive one is latched, as a limit value. Be sure to turn off the limit setting
(CFRFON = 0) when you set the limit value. If the limit was set with the limit setting on
(CFRFON = 1), result of computation is not assured.