Renesas Hitachi H8S/2191, Hardware Manual, Page: 250 / 1065

Rev. 2.0, 11/00, page 223 of 1037
Section 10 Clock Pulse Generator
10.1 Overview
This LSI has a built-in clock pulse generator (CPG) that generates the system clock (
φ
), the bus
master clock, and internal clocks.
The clock pulse generator consists of a system clock oscillator, a duty adjustment circuit, clock
selection circuit, medium-speed clock divider, subclock oscillator, and subclock division circuit.
10.1.1 Block Diagram
Figure 10.1 shows a block diagram of the clock pulse generator.
System
clock
oscillator
Duty
adjustment
circuit
Clock
selection
circuit
Medium-
speed clock
divider
Subclock
oscillator
Subclock
division
circuit
OSC1
OSC2
X1
X2
/16, /32, /64
w/2, w/4, w/8
SUB
or SUB
Timer A
count clock
Internal clock
To supporting modules
Bus master clock
To CPU
SUB ( w/2, w/4, w/8)
Figure 10.1 Block Diagram of Clock Pulse Generator
10.1.2 Register Configuration
The clock pulse generator is controlled by SBYCR and LPWRCR. Table 10.1 shows the register
configuration.
Table 10.1 CPG Registers
Name Abbreviation R/W Initial Value Address *
Standby control register SBYCR R/W H'00 H'FFEA
Low-power control
register LPWRCR R/W H'00 H'FFEB
Note:
*
Lower 16 bits of the address.