Renesas Hitachi H8S/2191, Hardware Manual

Page: 603 / 1065

Rev. 2.0, 11/00, page 576 of 1037
26.1.4 Register Configuration
Table 26.2 summarizes the registers of the A/D converter.
Table 26.2 A/D Converter Registers
Name Abbrev. R/W Size Initial Value Address
* 2
Software trigger A/D
result register H ADRH R Byte H'00 H'D130
Software trigger A/D
result register L ADRL R Byte H'00 H'D131
Hardware trigger A/D
result register H AHRH R Byte H'00 H'D132
Hardware trigger A/D
result register L AHRL R Byte H'00 H'D133
A/D control register ADCR R/W Byte H'40 H'D134
A/D control/status
register ADCSR R (W)
* 1
Byte H'01 H'D135
A/D trigger selection
register ADTSR R/W Byte H'FC H'D136
Port mode register 0 PMR0 R/W Byte H'00 H'FFCD
Notes: 1. Only 0 can be written in bits 7 and 6, to clear the flag. Bits 3 to 1 are read-only.
2. Lower 16 bits of the address.