Renesas Hitachi H8S/2191, Hardware Manual

Page: 687 / 1065

Rev. 2.0, 11/00, page 660 of 1037
(3) HSW Loop Stage Number Setting Register (HSLP)
0
*
1
*
R/W
2
*
R/W
3
*
4
*
R/W
5
*
6
*
7
R/W R/W R/W
LOB1
R/W
LOB2
*
R/W
LOB3 LOB0 LOA3 LOA2 LOA1 LOA0
Bit :
Initial value :
R/W :
Note: * Undetermined
HSLP sets the number of the loop stages when the HSW timing generator is in loop mode. It is
valid if bit 5 (LOP) of HSM2 is 1. Bits 7 to 4 set the number of FIFO2 stages. Bits 3 to 0 set the
number of FIFO1 stages.
HSLP is an 8-bit read/write register. It is not initialized by a reset, stand-by or module stop,
accordingly be sure to set the number of the stages when the loop mode is used.