Renesas Hitachi H8S/2191, Hardware Manual

Page: 129 / 1065

Rev. 2.0, 11/00, page 102 of 1037
6.2.3 IRQ Enable Register (IENR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0 0
7
R/W R/W R/W
IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
0
6
— —
— —
Bit :
Initial value :
R/W :
IENR is an 8-bit readable/writable register that controls enabling and disabling of interrupt
requests IRQ5 to IRQ0.
IENR is initialized to H'00 by a reset.
Bits 7 and 6: Reserved
Do not write 1 to them.
Bits 5 to 0: IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E)
These bits select whether IRQ5 to IRQ0 are enabled or disabled.
Bit n
IRQnE Description
0 IRQn interrupt disabled (Initial value)
1 IRQn interrupt enabled
(n = 5 to 0)