Renesas Hitachi H8S/2191, Hardware Manual

Page: 337 / 1065

Rev. 2.0, 11/00, page 310 of 1037
14.2.2 Timer J Control Register (TMJC)
0 1
0
2
0
R/W
3
(PS22)
*
—
(R/W)
*
—
4
0
R/W
5
0
6
0
7
R/W R/W
MON1
R/W
BUZZ0
0
R/W
BUZZ1 MON0 TMJ2IE TMJ1IE
1 1
Bit :
Initial value :
R/W :
Note:
*
Bit 0 is readable/writable only in the H8S/2194C series.
The timer J control register works to select the buzzer output frequency and to control
permission/prohibition of interrupts.
The TMJC is an 8-bit read/write register.
When reset, the TMJC is initialized to H'09.
Bits 7 and 6: Selecting the Buzzer Output (BUZZ1 or BUZZ0)
This bit works to select if using the buzzer outputs as the output signal through the BUZZ pin or
if using the monitor signals as the output signal through the BUZZ pin.
When setting is made to the monitor signals, choose the monitor signal using the MON1 bit and
MON0 bit.
Bit 7 Bit 6
BUZZ1 BUZZ0 Description
Frequency when
φ
= 10MHz
0
φ
/4096 (Initial value) 2.44 kHz 0
1
φ
/8192 1.22 kHz
0 Works to output monitor signals 1
1 Works to output BUZZ signals from the Timer J