Renesas Hitachi H8S/2191, Hardware Manual

Page: 355 / 1065

Rev. 2.0, 11/00, page 328 of 1037
15.3 Operation
The Timer L is an 8-bit up/down counter.
The inputting clock for the Timer L can be selected by the LMR2 to LMR0 bits of the LMR
from the choices of the internal clock (
φ
/128 and
φ
/64), DVCDG2, PB and REC-CTL.
The Timer L is provided with three different types of operation modes, namely, the compare
match clear mode when controlled to the up-counting function, the auto reloading mode when
controlled to the down-counting function and the interval timer mode.
Respective operation modes and operation methods will be explained below.
15.3.1 Compare Match Clear Operation
When the LMR3 bit of the LMR is cleared to 0, the Timer L will be controlled to the up-
counting function.
When any other values than H'00 are written into the RCR, the LTC will be cleared to H'00
simultaneously before starting counting up.
Figure 15.2 shows the clear timing of the LTC. When the LTC value and the RCR value match
(compare match), the LTC readings will be cleared to H'00 to resume counting from H'00.
Figure 15.3 indicated on the next page shows the compare match clear timing.
RCR
LTC
Write signal
1 state
N
H' 00
Figure 15.2 RCR Writing and LTC Clearing Timing Chart