Renesas Hitachi H8S/2191, Hardware Manual, Page: 627 / 1065

Rev. 2.0, 11/00, page 600 of 1037
(4) When the condition is not satisfied by Bcc instruction (Trap address at branch)
When the trap address is at the branch of the Bcc instruction and the condition is not satisfied
by the Bcc instruction and thus it fails to branch, transition is made into the address trap
interrupt after executing the next instruction (if the next instruction is that of 2 states or
more. If the next instruction is that of 1 state, after executing two instructions). The address
to be stacked is 0262.
Address bus
Interrupt
request
signal
Start of
exception
handling
025C 0262 0266 025E 0260 0264
025C BEQ NEXT:8
025E NOP
0260 NOP
0262 NOP
0264 NOP
0266 CMP.W R0, R1
0268 NOP
(NEXT = H'0266)
BEQ
execution
NOP
execu-
tion NOP
execu-
tion
*
BEQ
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
CMP
instruc-
tion
pre-fetch
* Trap setting address
The underlines address is the
one to be actually stacked.
NEXT:
Figure 27.9 When the Condition is Not Satisfied by Bcc Instruction
(Trap Address at Branch)