Renesas Hitachi H8S/2191, Hardware Manual, Page: 571 / 1065

Rev. 2.0, 11/00, page 544 of 1037
Bit 5: I
2
C Controller Reset (IICRST)
This bit controls the initialization of the internal state of the I
2
C bus interface. When the I
2
C bus
interface operating mode is hung because of communications error, and the IICRST bit is then
set to 1, the I
2
C bus interface controller is initialized of the internal state, and this allows the
internal state of the I
2
C bus interface to be initialized without making port settings or initializing
registers.
For the detail, refer to section 25.3.9, Initialization of Internal State.
The initialization is continuous and the I
2
C bus interface cannot operate, when the IICST bit
remains set to 1. Therefore, be sure to clear the IICST bit after setting it.
Bit 5
IICRST Description
0 I
2
C bus interface controller is not reset (Initial value)
1 I
2
C bus interface controller is reset
Bits 3: Flash Memory Control Resister Enable (FLSHE)
This bit selects the control resister of the flash memory. For details, refer to section 7.3.4 or
8.5.5, Serial Timer Control Resister.
Bits 4 and 2 to 0: Reserved