Renesas Hitachi H8S/2191, Hardware Manual

Page: 836 / 1065

Rev. 2.0, 11/00, page 809 of 1037
28.15.7 Sync Signal Detector Activation
The sync signal detector starts operation by release of reset, or by accepting input of a sync
signal after its transition from power-down mode to active mode and release of module stop.
The signal given to the detector is the polarity pulse assigned by the SYCT bit of the sync signal
control register (SYNCR). The detector starts operation even if this pulse was a noise pulse with
a width short of the regular width. The minimum pulse width which can activate the detector is
not constant depending on the internal operation of the input circuit. Accordingly, if the assured
activation of the detector is required, input a pulse with a width greater than 4/
φ
s (
φ
s = fosc/2
(Hz)). In such a case, care is required to noise, etc., because even a pulse with a width smaller
than 4
φ
/s may cause activation.