Renesas Hitachi H8S/2191, Hardware Manual

Page: 126 / 1065

Rev. 2.0, 11/00, page 99 of 1037
6.1.3 Pin Configuration
Table 6.1 summarizes the pins of the interrupt controller.
Table 6.1 Interrupt Controller Pins
Name Symbol I/O Function
Nonmaskable
interrupt
10,
Input Nonmaskable external interrupt; rising, falling, or
both edges can be selected
External interrupt
request
,54
Input Maskable external interrupts; rising, falling, or both
edges can be selected
External interrupt
requests 1 to 5
,54
to
,54
Input Maskable external interrupts: rising, or falling
edges can be selected
6.1.4 Register Configuration
Table 6.2 summarizes the registers of the interrupt controller.
Table 6.2 Interrupt Controller Registers
Name Abbreviation R/W Initial Value Address
* 1
System control register SYSCR R/W H'00 H'FFE8
IRQ edge select register IEGR R/W H'00 H'FFF0
IRQ enable register IENR R/W H'00 H'FFF1
IRQ status register IRQR R/ (W)
*
2
H'00 H'FFF2
Interrupt control register A ICRA R/W H'00 H'FFF3
Interrupt control register B ICRB R/W H'00 H'FFF4
Interrupt control register C ICRC R/W H'00 H'FFF5
Interrupt control register D ICRD R/W H'00 H'FFF6
Port mode register 1 PMR1 R/W H'00 H'FFCE
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, for flag clearing.