Renesas Hitachi H8S/2191, Hardware Manual

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Rev. 2.0, 11/00, page 543 of 1037
Bit 0: Acknowledge Bit (ACKB)
Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns
acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been
received, the acknowledge data set in this bit is sent to the transmitting device.
When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line
(returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal
software is read.
Bit 0
ACKB Description
0 Receive mode: 0 is output at acknowledge output timing (Initial value)
Transmit mode: Indicates that the receiving device has acknowledged the data
(signal is 0)
1 Receive mode: 1 is output at acknowledge output timing
Transmit mode: Indicates that the receiving device has not acknowledged the data
(signal is 1)
25.2.7 Serial/Timer Control Register (STCR)
7
—
0
—
6
IICX
0
R/W
5
IICRST
0
R/W
4
—
0
—
3
FLSHE
0
R/W
0
—
0
—
2
—
0
—
1
—
0
—
Bit :
Initial value :
R/W :
STCR is an 8-bit readable/writable register that controls the I
2
C bus interface operating mode.
STCR is initialized to H'00 by a reset.
Bit 7: Reserved
Bit 6: I
2
C Transfer Select (IICX)
This bit, together with bits CKS2 to CKS0 in ICMR of I
2
C, selects the transfer rate in master
mode. For details, see section 25.2.4, I
2
C Bus Mode Register (ICMR).