Renesas Hitachi H8S/2191, Hardware Manual, Page: 624 / 1065

Rev. 2.0, 11/00, page 597 of 1037
27.3.2 Enable
The address trap function becomes valid after executing one instruction following the setting of
the enable bit of the address trap control register (TRCR) to 1.
029C BSET #0, @TRCR
*
029E MOV.W R0, R1
02A0 MOV.B R1L, R3H
02A2 NOP
02A4 CMP.W R0, R1
02A6 NOP
* Trap setting address
After executing the MOV instruction,
the address trap interrupt does not
arise, and the next instruction is
executed.
Figure 27.5 Enable
27.3.3 Bcc Instruction
(1) When the condition is satisfied by Bcc instruction (8-bit displacement)
If the trap address is the next instruction to the Bcc instruction and the condition is satisfied
by the Bcc instruction and then branched, transition is made to the address trap interrupt after
executing the instruction at the branch. The address to be stacked is 02A8.
Address bus
Interrupt
request
signal
BEQ
execu-
tion CMP
execu-
tion
029C 02A8 029E 02A6 02AA
029C BEQ NEXT:8
029E NOP
02A0 NOP
02A2 NOP
02A4 NOP
02A6 CMP.W R0, R1
02A8 NOP
(NEXT = H'02A6)
*
Start of
exception
handling BEQ
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
CMP
instruc-
tion
pre-fetch
*
Trap setting address
The underlines address is the
one to be actually stacked.
Figure 27.6 When the Condition is Satisfied by Bcc Instruction (8-bit Displacement)