Renesas Hitachi H8S/2191, Hardware Manual

Page: 777 / 1065

Rev. 2.0, 11/00, page 750 of 1037
Bits 3: Clock Source Selection Bit (CCS)
Selects clock source of CTL.
Bit 3
CCS Description
0
φ
s (Initial value)
1
φ
s/2
Bit 2: Long CTL Bit (LCTL)
Sets the long CTL detection mode.
Bit 2
LCTL Description
0 Clock source (CCS) operates at the setting value (Initial value)
1 Clock source (CCS) operates for further 8-division after operating at the setting
value
Bit 1: CTL Undetected Bit (UNCTL)
Indicates the CTL pulse detection status at the CTL input amplifier sensitivity set at the CTL
gain control register (CTLGR).
Bit 1
UNCTL Description
0 Detected (Initial value)
1 Undetected
Bit 0: Mode Selection Bit (SLWM)
Selects CTL mode.
Bit 0
SLWM Description
0 Normal mode (Initial value)
1 Slow mode