Renesas Hitachi H8S/2191, Hardware Manual, Page: 110 / 1065

Rev. 2.0, 11/00, page 83 of 1037
4.7 Watch Mode
4.7.1 Watch Mode
If a SLEEP instruction is executed in high-speed mode, medium-speed mode or subactive mode
when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the TMA3
bit in TMA (Timer A) is set to 1, the CPU makes a transition to watch mode.
In this mode, the CPU and all on-chip supporting modules except Timer A stop. As long as the
prescribed voltage is supplied, the contents of some of the CPU's internal registers and on-chip
RAM are retained, and I/O ports are placed in the high-impedance state.
4.7.2 Clearing Watch Mode
Watch mode is cleared by an interrupt (Timer A interrupt, NMI pin, or pin
,54 to ,54), or by
means of the
5(6 pin.
(1) Clearing with an Interrupt
When an interrupt request signal is input, watch mode is cleared and a transition is made to
high-speed mode or medium-speed mode if the LSON bit in LPWRCR is cleared to 0, or to
subactive mode if the LSON bit is set to 1. When making a transition to medium-speed
mode, after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are
supplied to the entire chip, and interrupt exception handling is started.
Watch mode cannot be cleared with an
,54 to ,54 interrupt if the corresponding enable
bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the
relevant interrupt has been disabled by the interrupt enable register or masked by the CPU.
See section 4.6.3, Setting Oscillation Settling Time after Clearing Standby Mode, for the
oscillation settling time setting when making a transition from watch mode to high-speed
mode.
(2) Clearing with the
5(6 Pin
See (2) Clearing with the
5(6 Pin in section 4.6.2, Clearing Standby Mode.