Renesas Hitachi H8S/2191, Hardware Manual

Page: 361 / 1065

Rev. 2.0, 11/00, page 334 of 1037
16.2 Descriptions of Respective Registers
16.2.1 Timer R Mode Register 1 (TMRM1)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/W R/W R/W
RLD
R/W
AC/BR
0
R/W
CLR2 RLCK PS21 PS20 RLD/CAP CPS
Bit :
Initial value :
R/W :
The timer R mode register 1 (TMRM1) works to control the acceleration and braking processes
and to select the inputting clock for the TMRU-2. This is an 8-bit read/write register.
When reset, the TMRM1 is initialized to H'00.
Bit 7: Selecting Clearing/Not Clearing of TMRU-2 (CLR2)
This bit is used for selecting if the TMRU-2 counter reading is to be cleared or not as it is
captured.
Bit 7
CLR2 Description
0 TMRU-2 counter reading is not to be cleared as soon as it is captured. (Initial value)
1 TMRU-2 counter reading is to be cleared as soon as it is captured
Bit 6: Selecting the Acceleration/Braking Processing (AC/BR)
This bit works to control occurrences of interrupt requests to detect completion of acceleration
or braking while the capstan motor is making intermittent revolutions.
For more information, see section 16.3.6, Acceleration and Braking of the Capstan Motor.
Bit 6
AC/BR Description
0 Acceleration (Initial value)
1 Braking