Renesas Hitachi H8S/2191, Hardware Manual

Page: 592 / 1065

Rev. 2.0, 11/00, page 565 of 1037
25.3.9 Initialization of Internal State
This I
2
C is capable of forcibly initializing internal state of I
2
C if deadlock develops during
communication.
The initialization is done by setting IICRST bit in STCR register, or clearing ICE bit.
For details, see section 25.2.7, Serial/Time control Register (STCR).
(1) Range of Initialization
The following is initialized by this function:
•
Internal flags of TDRE and RDRF
•
Programmable logic controller for signal receiving and sending.
•
Internal latches used for holding outputs from SCL and SDA pins (wait, clock, data output,
etc.).
The following is not initialized by this function:
•
Register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, and STCR).
•
Internal latches employed for maintaining data read from the registers which is used for
setting or clearing flags on ICMR, ICCR, and ICSR registers.
•
Values on the ICMR register bit counters (BC2 to BC0).
•
Interrupt factors currently generated (interrupt factors transferred to the interrupt controller).
(2) Precautions on Initialization
•
Interrupt flags and interrupt factors are not cleared by this function. Thus, you need to clear
them own as needed.
•
Other register flags are not basically cleared, too. Thus, you need to clear them as needed.
•
When this I
2
C is initialized with IICRST bit, write data specified by IICRST bit is
maintained. When clearing I
2
C, set IICRST bit once, then clear it using the MOV
instruction. The I
2
C cannot operate with the IICRST bit set to 1. Don't try to use bit
operation instructions such as BCLR.
•
If you try to clear a flag while data sending or receiving is taking place, I
2
C module stops
sending or receiving at that moment and frees the SCL and SDA pins. When resuming the
communication, initialize registers as needed so that the system communication capability
may function as intended.
Clear function of this module does not directly rewrite value of BBSY bit. However, depending
on state of SCL and SDA pins and the timing in which they are made free, BBSY bit can be
cleared. Other bits and flags can also be affected by status change.