Renesas Hitachi H8S/2191, Hardware Manual

Page: 835 / 1065

Rev. 2.0, 11/00, page 808 of 1037
(2) Operation to Detect Noise
The noise detector considers an irregular pulse of the composite sync signal (Csync) and a
chip of a pulse of the horizontal sync signal within a frame as noise. The noise counter takes
counts of the irregular pulses during the High period of the noise detection window and the
chips and drop-outs of the horizontal sync signal pulses during the Low period. Also, it
counts more than one irregular pulses as one. The noise counter is cleared at every frame
(Vsync is detected twice).
The equivalent pulse contained in 9H of the vertical sync signal is counted also as an
irregular pulse.
It sets the noise detection flag (NOIS) in the sync signal control register (SYNCR) at 1 if the
count of the irregular the count of the pulse chips and drop-outs of the horizontal
sync signal > 4
×
(value of NDR7 to NDR0).
See section 28.15.5 (7), Sync Signal Control Register (SYNCR) for the NOIS bit.
Figure 28.76 shows the operation of the noise detection.
Csync
Noise detection
window
Noise detection
flag (NOIS)
Noise counter
Noise detection
level
Noise detection
flag is set.
NOIS : Bit 2 of the sync signal control register (SYNCR)
Noise
Figure 28.76 Operation of the Noise Detection