Renesas Hitachi H8S/2191, Hardware Manual

Page: 531 / 1065

Rev. 2.0, 11/00, page 504 of 1037
Bits 4 and 3: Transmit Data Interval Select 1 and 0 (GAP1, GAP0)
When an internal clock is used, data can be transmitted at 1-byte intervals. During that time, the
SCK2 pin retains the high level. When data is transmitted without intervals, the STRB signal
retains the low level.
Bit 4 Bit 3
GAP1 GAP0 Description
0 0 Data transmission without intervals (Initial value)
0 1 Data intervals: 8 clocks
1 0 Data intervals: 24 clocks
1 1 Data intervals: 56 clocks
Bits 2 to 0: Transfer Clock Select 2 to 0 (CKS2 to CKS0)
Selects transfer clock.
Bit 2 Bit 1 Bit 0 Transfer clock cycle
CKS2 CKS1 CKS0
SCK2
pin Clock
source Prescaler division
ratio
φ
= 10 MHz
φ
= 5 MHz
0 0 0
φ
/256 (Initial value) 25.6
µ
s 51.2
µ
s
0 0 1
φ
/64 6.4
µ
s 12.8
µ
s
0 1 0
φ
/32 3.2
µ
s 6.4
µ
s
0 1 1
φ
/16 1.6
µ
s 3.2
µ
s
1 0 0
φ
/8 0.8
µ
s 1.6
µ
s
1 0 1
φ
/4 0.4
µ
s 0.8
µ
s
1 1 0
SCK2
output Prescaler
S
φ
/2

0.4
µ
s
1 1 1 SCK2
input External
clock
  
24.2.4 Serial Control Status Register 2 (SCSR2)
0
0
1
0
R/(W)
*
2
0
R/(W)
*
3
0
4
0
R/W
5 6
— —
— —
7
R/W R/(W)
*
SOL
R/(W)
*
TEI ORER WT ABT STF
0 1 1
Note:
*
Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
The SCSR2 is an 8-bit register that indicates the SCI2's state of operation and error.
The SCSR2 is initialized to H'60 by a reset.