Renesas Hitachi H8S/2191, Hardware Manual

Page: 614 / 1065

Rev. 2.0, 11/00, page 587 of 1037
26.3 Interface to Bus Master
ADR and AHR are 16-bit registers, but the data bus to the bus master is only 8 bits wide.
Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte
is accessed via a temporary register (TEMP).
A data reading from ADR and AHR is performed as follows. When the upper byte is read, the
upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP.
Next, when the lower byte is read, the TEMP contents are transferred to the CPU.
When reading ADR and AHR, always read the upper byte before the lower byte. It is possible to
read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 26.3 shows the data flow for ADR access. The data flow for AHR access is the same.
Bus master
(H'AA)
ADRH
(H'AA)
ADRL
(H'40)
Lower byte read
Bus master
(H'40)
ADRH
(H'AA)
ADRL
(H'40)
TEMP
(H'40)
TEMP
(H'40)
Module data bus
Module data bus
Bus
interface
Bus
interface
Upper byte read
Figure 26.3 ADR Access Operation (Reading H'AA40)