Renesas Hitachi H8S/2191, Hardware Manual, Page: 446 / 1065

Rev. 2.0, 11/00, page 419 of 1037
20.2.2 12-Bit PWM Data Registers (CPWDR, DPWDR)
(1) CPWDR
1
0
R/W
CPWDR1
0
0
R/W
CPWDR0
3
0
R/W
CPWDR3
2
0
R/W
CPWDR2
5
0
R/W
CPWDR5
4
0
R/W
CPWDR4
7
0
R/W
CPWDR7
6
0
R/W
CPWDR6
9
0
R/W
CPWDR9
8
0
R/W
CPWDR8
11
0
R/W
CPWDR11
10
0
R/W
CPWDR10
12
1
13
1
14
1
15
— — — —
— — — —
1
Bit :
Initial value :
R/W :
(2) DPWDR
1
0
R/W
DPWDR1
0
0
R/W
DPWDR0
3
0
R/W
DPWDR3
2
0
R/W
DPWDR2
5
0
R/W
DPWDR5
4
0
R/W
DPWDR4
7
0
R/W
DPWDR7
6
0
R/W
DPWDR6
9
0
R/W
DPWDR9
8
0
R/W
DPWDR8
11
0
R/W
DPWDR11
10
0
R/W
DPWDR10
12
1
13
1
14
1
15
1
— — — —
— — — —
Bit :
Initial value :
R/W :
The 12-bit PWM data registers (CPWDR and DPWDR) are 12-bit readable/writable registers
in which the data to be converted to PWM output is written.
The data in these registers is converted to PWM output only when bit SF/DF of the
corresponding control register is set to 1. The error data from the digital filter circuit is
written in the data register, and then modulated by PWM. At this time, the error data from
the digital filter circuit can be monitored by reading the data register.
These registers can be accessed by word only, and cannot be accessed by byte. Byte access
gives unassured results.
CPWDR and DPWDR are initialized to H'F000 by a reset, or in sleep mode, standby mode,
watch mode, subactive mode, subsleep mode, or module stop mode of the servo circuit.