Renesas Hitachi H8S/2191, Hardware Manual

Page: 807 / 1065

Rev. 2.0, 11/00, page 780 of 1037
28.14 Frequency Dividers
28.14.1 Overview
On-chip frequency dividers are provided for the pulse signal picked up from the control track
during playback (PB-CTL signal), and the pulse signal received from the capstan motor (CFG
signal). An on-chip noise canceller is provided for the drum motor pulse signal (DFG signal).
The CTL frequency divider generates a CTL divided control signal (DVCTL) from the PB-CTL
signal, for use in capstan phase control during high-speed search, for example. The CFG
frequency divider generates two divided signals (DVCFG for speed control and DVCFG2 for
phase control) from the CFG signal. The DFG noise canceller is a circuit which considers a
signal less than 2
φ
as noise and masks it.
28.14.2 CTL Frequency Divider
(1) Block Diagram
Figure 28.63 shows a block diagram of the CTL frequency divider.
EXCTL
PB-CTL
,
DVCTL
UDF
R/W W
(8bit)
R/W
Internal bus
CEX
CTL division register
Down counter (8 bits)
CEG
Edge
detector
· CTVC
· CTLR
· CTVC
Figure 28.63 CTL Frequency Divider
(2) Register Configuration
•
Register configuration
Table 28.22 shows the register configuration of the CTL dividers.
Table 28.22 Register Configuration
Name Abbrev. R/W Size Initial Value Address
DVCTL control register CTVC R/W Byte Undefined H'FD098
CTL division register CTLR W Byte H'00 H'FD099