Renesas Hitachi H8S/2191, Hardware Manual

Page: 988 / 1065

Rev. 2.0, 11/00, page 961 of 1037
H'D106: Timer Control Register X TCRX: Timer X1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
R/W R/W
IEDGB
0
R/W
IEDGA
R/W
IEDGD
R/W
IEDGC
R/W
BUFEB
R/W
BUFEA CKS0
R/W
CKS1
Capture at falling edge of input capture input A
Capture at rising edge of input capture input A
0
1
Input capture edge select A
Capture at falling edge of input capture input B
Capture at rising edge of input capture input B
0
1
Input capture edge select B
Capture at falling edge of input capture input C
Capture at rising edge of input capture input C
0
1
Input capture edge select C
Capture at falling edge of input capture input D
Capture at rising edge of input capture input D
0
1
Input capture edge select D
ICRC is not used as buffer register for ICRB
ICRC is used as buffer register for ICRB
0
1
Buffer enable B
ICRC is not used as buffer register for ICRA
ICRC is used as buffer register for ICRA
0
1
Buffer enable A
Clock selct bit
Clock select
0 0
CKS0 CKS1
1 0
0 1
Internal clock: count at
φ
/4
Internal clock: count at
φ
/16
Internal clock: count at
φ
/64
1 1 DVCFG: Edge detection p
ulse selected by CFG
frequency division timer
Bit :
Initial value :
R/W :