Renesas Hitachi H8S/2191, Hardware Manual

Page: 682 / 1065

Rev. 2.0, 11/00, page 655 of 1037
Bit 3: FIFO2 Overwrite Flag (OVWB)
If a write is attempted when the timing pattern data and the output pattern data of FIFO2 are full
(FLB bit = 1), the write operation becomes invalid, an interrupt is generated, the OVWB flag is
set to 1, and the write data is lost. Wait until space becomes available in the FIFO2, then write
again.
Write 0 to clear the OVWB flag, because it is not cleared automatically.
Bit 3
OVWB Description
0 Normal operation (Initial value)
1 Indicates that a write in FIFO2 was attempted when FIFO2 was full. Clear this flag
by 0 writing
Bit 2: FIFO1 Overwrite Flag (OVWA)
If a write is attempted when the timing pattern data and the output pattern data of FIFO1 are full
(FLA bit = 1), the write operation becomes invalid, an interrupt is generated, the OVWA flag is
set to 1, and the write data is lost. Wait until space becomes available in the FIFO1, then write
again.
Write 0 to clear the OVWA flag, because it is not cleared automatically.
Bit 2
OVWA Description
0 Normal operation (Initial value)
1 Indicates that a write in FIFO1 was attempted when FIFO1 was full. Clear this flag
by 0 writing
Bit 1: FIFO2 Pointer Clear (CLRB)
Clears the FIFO2 write position pointer. After 1 is written, the bit immediately reverts to 0.
Writing 0 in this bit has no effect.
Bit 1
CLRB Description
0 Normal operation (Initial value)
1 Clears the FIFO2 pointer