NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1036 / 1379

GPIOx_PDDR field descriptions (continued)
Field Description
40.3 FGPIO memory map and register definition
The GPIO registers are also aliased to the IOPORT interface on the Cortex-M0+ from
address 0xF800_0000.
Accesses via the IOPORT interface occur in parallel with any instruction fetches and will
therefore complete in a single cycle. This aliased Fast GPIO memory map is called
FGPIO.
Any read or write access to the FGPIO memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states, except
error accesses which complete with one wait state.
FGPIO memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
F800_0000 Port Data Output Register (FGPIOA_PDOR) 32 R/W 0000_0000h 40.3.1/1036
F800_0004 Port Set Output Register (FGPIOA_PSOR) 32
W
(always
reads 0)
0000_0000h 40.3.2/1037
F800_0008 Port Clear Output Register (FGPIOA_PCOR) 32
W
(always
reads 0)
0000_0000h 40.3.3/1037
F800_000C Port Toggle Output Register (FGPIOA_PTOR) 32
W
(always
reads 0)
0000_0000h 40.3.4/1038
F800_0010 Port Data Input Register (FGPIOA_PDIR) 32 R 0000_0000h 40.3.5/1038
F800_0014 Port Data Direction Register (FGPIOA_PDDR) 32 R/W 0000_0000h 40.3.6/1039
40.3.1 Port Data Output Register (FGPIOx_PDOR)
This register configures the logic levels that are driven on each general-purpose output
pins.
Address: F800_0000h base + 0h offset = F800_0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PDO
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FGPIO memory map and register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
1036 NXP Semiconductors