NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1217 / 1379

Offset Register Width
(In bits)
Access Reset value
400A50A0h TRNG0 Security Configuration (TRNG0_SEC_CFG) 32 RW 00000000h
400A50A4h TRNG0 Interrupt Control (TRNG0_INT_CTRL) 32 RW FFFFFFFFh
400A50A8h TRNG0 Mask (TRNG0_INT_MASK) 32 RW 00000000h
400A50ACh TRNG0 Interrupt Status (TRNG0_INT_STATUS) 32 RW 00000000h
400A50F0h TRNG0 Version ID (MS) (TRNG0_VID1) 32 RO 00300100h
400A50F4h TRNG0 Version ID (LS) (TRNG0_VID2) 32 RO 00000000h
1. Reset occurs at POR, and when TRNG0_MCTL[RST_DEF] is written to 1.
48.1.3.3.2 TRNG0 Miscellaneous Control (TRNG0_MCTL)
48.1.3.3.2.1 Address
Register Offset
TRNG0_MCTL 400A5000h
48.1.3.3.2.2 Function
This register is intended to be used for programming, configuring and testing the RNG. It
is the main register to read/write, in order to enable Entropy generation, to stop entropy
generation and to block access to entropy registers. This is done via the special
TRNG_ACC and PRGM bits below.
The TRNG0 Miscellaneous Control Register is a read/write register used to control the
RNG's True Random Number Generator (TRNG) access, operation and test.
NOTE
Note that in many cases two RNG registers share the same
address, and a particular register at the shared address is
selected based upon the value in the PRGM field of the
TRNG0_MCTL register.
Chapter 48 SA-TRNG Standalone
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1217