NXP Semiconductors K32 L2A Series, Reference Manual, Page: 741 / 1379

Table 27-4. Master Interrupts and DMA Requests (continued)
Flag Description Interrupt DMA Request Low Power Wakeup
wrong time, or Master
was transmitting data
but received different
data than what was
transmitted.
FEF Master expecting
START condition in
command FIFO and
next entry in FIFO is not
START condition.
Y N Y
PLTF Pin low timeout is
enabled and SCL (or
SDA if configured) is
low for longer than the
configured timeout.
Y N Y
DMF Received data matches
the configured data
match, and receive data
not discarded due to
command FIFO entry.
Y N Y
MBF LPI2C master is busy
transmitting/receiving
data.
N N N
BBF LPI2C master is
enabled and activity
detected on I2C bus,
but STOP condition has
not been detected and
bus idle timeout (if
enabled) has not
occurred.
N N N
27.3.4.2 Slave mode
The following table illustrates the slave mode sources that can generate the LPI2C slave
interrupt and the LPI2C slave transmit/receive DMA requests.
Table 27-5. Slave Interrupts and DMA Requests
Flag Description Interrupt DMA Request Low Power Wakeup
TDF Data can be written to
transmit data register. Y TX Y
RDF Data can be read from
the receive data
register.
Y RX Y
Table continues on the next page...
Chapter 27 Low Power Inter-Integrated Circuit (LPI2C)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 741