NXP Semiconductors K32 L2A Series, Reference Manual, Page: 71 / 1379

Signal
multiplexing
Module signals
Register
access
CMP
Peripheral
bridge 0
Other
peripherals
Figure 3-7. CMP configuration
Table 3-13. Reference links to related information
Topic Related module Reference
Full description Comparator (CMP) Comparator
System memory map — System memory map
Clocking — Clock distribution
Power management — Power management
Signal multiplexing Port control Signal multiplexing
3.7.2.1 CMP instantiation information
The device includes two high-speed comparators each with two 8-input multiplexers for
both the inverting and non-inverting inputs of the comparator. Each CMP input channel
connects to both muxes. Two of the channels are connected to internal sources, leaving
resources to support up to 6 input pins. See the channel assignment table for a summary
of CMP input connections for this device.
The CMPs also include one 6-bit DAC with a 64-tap resistor ladder network, which
provides a selectable voltage reference for applications where voltage reference is needed
for an internal connection to the CMP.
The CMPs can be optionally on in all modes except VLLS0.
3.7.2.2 CMP connections
The following table shows the fixed internal connections to the CMPs.
Chapter 3 Chip Configuration
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 71