NXP Semiconductors K32 L2A Series, Reference Manual, Page: 994 / 1379

38.2.3.4 Debug mode
In Debug mode, PORT operates normally.
38.3 External signal description
The table found here describes the PORT external signal.
Table 38-2. Signal properties
Name Function I/O Reset Pull
PORTx[31:0] External interrupt I/O 0 -
NOTE
Not all pins within each port are implemented on each device.
38.4 Detailed signal description
The table found here contains the detailed signal description for the PORT interface.
Table 38-3. PORT interface—detailed signal description
Signal I/O Description
PORTx[31:0] I/O External interrupt.
State meaning
Asserted—pin is logic 1.
Negated—pin is logic 0.
Timing Assertion—may occur at any time and can assert
asynchronously to the system clock.
Negation—may occur at any time and can assert
asynchronously to the system clock.
38.5 Memory map and register definition
Any read or write access to the PORT memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states.
External signal description
K32 L2A Reference Manual, Rev. 2, 01/2020
994 NXP Semiconductors