NXP Semiconductors K32 L2A Series, Reference Manual, Page: 335 / 1379

Table 15-2. CAU commands (continued)
Type
Command
name
Description
CMD
Operation
8 7 6 5 4 3 2 1 0
Direct load AESR AES Shift Rows 0x0E0 ShiftRows(CA0-CA3)
→
CA0-
CA3
Direct load AESIR AES Inv Shift Rows 0x0F0 InvShiftRows(CA0-CA3)
→
CA0-CA3
Direct load DESR DES Round 0x10 IP FP KS[1:0] DES Round(CA0-CA3)
→
CA0-CA3
Direct load DESK DES Key Setup 0x11 0 0 CP DC DES Key Op(CA0-CA1)
→
CA0-CA1
Key Parity Error & CP
→
CASR[1]
Direct load HASH Hash Function 0x12 0 HF[2:0] Hash Func(CA1-
CA3)+CAA
→
CAA
Direct load SHS Secure Hash Shift 0x130 CAA <<< 5
→
CAA,
CAA
→
CA0, CA0
→
CA1,
CA1 <<< 30
→
CA2,
CA2
→
CA3, CA3
→
CA4
Direct load MDS Message Digest Shift 0x140 CA3
→
CAA, CAA
→
CA1,
CA1
→
CA2, CA2
→
CA3,
Direct load SHS2 Secure Hash Shift 2 0x150 CAA
→
CA0, CA0
→
CA1,
CA1
→
CA2, CA2
→
CA3,
CA3 + CA8
→
CA4,
CA4
→
CA5, CA5
→
CA6,
CA6
→
CA7
Direct load ILL Illegal Command 0x1F0 0x1
→
CASR[IC]
15.6.3.1 Coprocessor No Operation (CNOP)
The CNOP command is the coprocessor no-op. It is issued by the CAU and consumes a
location in the CAU FIFO, but has no effect on any CAU register.
15.6.3.2 Load Register (LDR)
The LDR command loads CAx with the source data specified by the write data.
Chapter 15 Cryptographic Acceleration Unit (CAU)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 335