NXP Semiconductors K32 L2A Series, Reference Manual, Page: 490 / 1379

EMVSIMx_CTRL field descriptions (continued)
Field Description
This bit enables the calculation of the 16-bit CRC value for both receiver and transmitter. The result of the
calculation is continuously compared to the expected remainder and reflected in the CRC_OK bit in the
RX_STATUS register. Clearing this bit resets the current CRC residual value in the EMV SIM hardware.
0 16-bit Cyclic Redundancy Checking disabled (default)
1 16-bit Cyclic Redundancy Checking enabled
28
LRC_EN
LRC Enable
This bit enables the calculation of the 8-bit LRC value for both receiver and transmitter. The result of the
calculation is continuously compared to zero and reflected in the LRC_OK bit in the RX_STATUS register.
Clearing this bit resets the current LRC value in the EMV SIM hardware.
0 8-bit Linear Redundancy Checking disabled (default)
1 8-bit Linear Redundancy Checking enabled
27
CWT_EN
Character Wait Time Counter Enable
Enables the character wait time counter. Clearing this bit resets the counter to zero.
0 Character Wait time Counter is disabled (default)
1 Character Wait time counter is enabled
26
CRC_IN_FLIP
CRC Input Byte's Bit Reversal or Flip Control
This bit control whether the bits in the CRC input byte will be reversed before CRC calculation or not.
When set to '1', the bits within the input byte for CRC will change from 7:0 to 0:7. For CCITT CRC
calculation, this bit should be set to '1'. For any other CRC using same polynomial, this bit can be set
accordingly.
0 Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default)
1 Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation
25
CRC_OUT_FLIP
CRC Output Value Bit Reversal or Flip
This bit control whether the bits in the CRC output bytes will be reversed or not. When set to '1', the bits
within the two bytes for CRC Output will change from 15:0 to {8:15,0:7}. For CCITT CRC calculation, this
bit should be set to '1'. For any other CRC using same polynomial, this bit can be set accordingly.
0 Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default)
1 Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7}
24
INV_CRC_VAL
Invert bits in the CRC Output Value
This bit control whether the bits within the CRC Output value will be inverted (1's complement) or not. For
CCITT CRC calculation, this bit should be set to '1'. For any other CRC using same polynomial, this bit
can be set accordingly.
0 Bits in CRC Output value will not be inverted.
1 Bits in CRC Output value will be inverted. (default)
23–21
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
20
TX_DMA_EN
Transmit DMA Enable
Enables assertion of DMA write request when Transmit FIFO is empty. Request is held asserted till
Transmit FIFO reaches the programmed data threshold value. Transmit Data Threshold Interrupt will not
be generated when this bit is asserted.
Table continues on the next page...
Memory Map and Registers
K32 L2A Reference Manual, Rev. 2, 01/2020
490 NXP Semiconductors