NXP Semiconductors K32 L2A Series Reference Manual Download Page 387

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DAC memory map

Absolute

address

(hex)

Register name

Width

(in bits)

Access Reset value

Section/

page

4006_A000 DAC Data Low Register (DAC0_DAT0L)

R/W

00h

18.4.1/388

4006_A001 DAC Data High Register (DAC0_DAT0H)

R/W

00h

18.4.2/388

4006_A002 DAC Data Low Register (DAC0_DAT1L)

R/W

00h

18.4.1/388

4006_A003 DAC Data High Register (DAC0_DAT1H)

R/W

00h

18.4.2/388

4006_A004 DAC Data Low Register (DAC0_DAT2L)

R/W

00h

18.4.1/388

4006_A005 DAC Data High Register (DAC0_DAT2H)

R/W

00h

18.4.2/388

4006_A006 DAC Data Low Register (DAC0_DAT3L)

R/W

00h

18.4.1/388

4006_A007 DAC Data High Register (DAC0_DAT3H)

R/W

00h

18.4.2/388

4006_A008 DAC Data Low Register (DAC0_DAT4L)

R/W

00h

18.4.1/388

4006_A009 DAC Data High Register (DAC0_DAT4H)

R/W

00h

18.4.2/388

4006_A00A DAC Data Low Register (DAC0_DAT5L)

R/W

00h

18.4.1/388

4006_A00B DAC Data High Register (DAC0_DAT5H)

R/W

00h

18.4.2/388

4006_A00C DAC Data Low Register (DAC0_DAT6L)

R/W

00h

18.4.1/388

4006_A00D DAC Data High Register (DAC0_DAT6H)

R/W

00h

18.4.2/388

4006_A00E DAC Data Low Register (DAC0_DAT7L)

R/W

00h

18.4.1/388

4006_A00F DAC Data High Register (DAC0_DAT7H)

R/W

00h

18.4.2/388

4006_A010 DAC Data Low Register (DAC0_DAT8L)

R/W

00h

18.4.1/388

4006_A011 DAC Data High Register (DAC0_DAT8H)

R/W

00h

18.4.2/388

4006_A012 DAC Data Low Register (DAC0_DAT9L)

R/W

00h

18.4.1/388

4006_A013 DAC Data High Register (DAC0_DAT9H)

R/W

00h

18.4.2/388

4006_A014 DAC Data Low Register (DAC0_DAT10L)

R/W

00h

18.4.1/388

4006_A015 DAC Data High Register (DAC0_DAT10H)

R/W

00h

18.4.2/388

4006_A016 DAC Data Low Register (DAC0_DAT11L)

R/W

00h

18.4.1/388

4006_A017 DAC Data High Register (DAC0_DAT11H)

R/W

00h

18.4.2/388

4006_A018 DAC Data Low Register (DAC0_DAT12L)

R/W

00h

18.4.1/388

4006_A019 DAC Data High Register (DAC0_DAT12H)

R/W

00h

18.4.2/388

4006_A01A DAC Data Low Register (DAC0_DAT13L)

R/W

00h

18.4.1/388

4006_A01B DAC Data High Register (DAC0_DAT13H)

R/W

00h

18.4.2/388

4006_A01C DAC Data Low Register (DAC0_DAT14L)

R/W

00h

18.4.1/388

4006_A01D DAC Data High Register (DAC0_DAT14H)

R/W

00h

18.4.2/388

4006_A01E DAC Data Low Register (DAC0_DAT15L)

R/W

00h

18.4.1/388

4006_A01F DAC Data High Register (DAC0_DAT15H)

R/W

00h

18.4.2/388

4006_A020 DAC Status Register (DAC0_SR)

R/W

02h

18.4.3/388

4006_A021 DAC Control Register (DAC0_C0)

R/W

00h

18.4.4/389

4006_A022 DAC Control Register 1 (DAC0_C1)

R/W

00h

18.4.5/391

4006_A023 DAC Control Register 2 (DAC0_C2)

R/W

0Fh

18.4.6/392

Chapter 18 12-bit Digital-to-Analog Converter (DAC)

K32 L2A Reference Manual, Rev. 2, 01/2020

NXP Semiconductors

387

Summary of Contents for K32 L2A Series

Page 1: ...K32 L2A Reference Manual K32L2A41VLL1A K32L2A31VLL1A K32L2A41VLH1A K32L2A31VLH1A Document Number K32L2AxRM Rev 2 01 2020...

Page 2: ...K32 L2A Reference Manual Rev 2 01 2020 2 NXP Semiconductors...

Page 3: ...A introduction 45 2 3 Feature Summary 45 2 4 Block Diagram 49 Chapter 3 Chip Configuration 3 1 Introduction 51 3 2 Clock gating 51 3 3 Module to Module Interconnects 52 3 3 1 Interconnection overview...

Page 4: ...ister File Configuration 66 3 6 Security 67 3 6 1 CAU Configuration 67 3 7 Analog 68 3 7 1 16 bit SAR ADC configuration 68 3 7 2 CMP configuration 70 3 7 3 VREF 72 3 7 4 12 bit DAC configuration 74 3...

Page 5: ...emory Maps 97 4 4 1 Flash Memory Map 97 4 5 SRAM Memory Map 98 4 6 Bit Manipulation Engine 98 4 7 Peripheral bridge AIPS Lite memory map 99 4 7 1 AIPS0 Peripheral Slot Assignments 99 4 7 2 AIPS1 Perip...

Page 6: ...r reset 120 5 13 Clock gating 121 5 14 Flash Memory Clock 121 Chapter 6 Reset and Boot 6 1 Introduction 123 6 2 Reset 124 6 2 1 Power on reset POR 124 6 2 2 System reset sources 124 6 2 3 MCU resets 1...

Page 7: ...2 Flash security 147 Chapter 9 Debug 9 1 Introduction 149 9 2 Debug port pin descriptions 149 9 3 Debug and Trace Block diagram 150 9 4 SWD status and control registers 151 9 4 1 MDM AP Control Regist...

Page 8: ...Features 175 11 1 2 Block diagram 176 11 2 ADC signal descriptions 177 11 2 1 Analog Power VDDA 178 11 2 2 Analog Ground VSSA 178 11 2 3 Voltage Reference Select 178 11 2 4 Analog Channel Inputs ADx...

Page 9: ...ral Calibration Value Register ADCx_CLMD 198 11 3 19 ADC Minus Side General Calibration Value Register ADCx_CLMS 198 11 3 20 ADC Minus Side General Calibration Value Register ADCx_CLM4 199 11 3 21 ADC...

Page 10: ...on 228 Chapter 13 Bit Manipulation Engine2 BME2 13 1 Introduction 229 13 1 1 Features 230 13 1 2 Modes of operation 230 13 2 Memory map and register definition 230 13 3 Functional description 231 13 3...

Page 11: ...eripheral 298 14 4 4 LPUART Peripheral 307 14 4 5 USB peripheral 309 14 5 Get SetProperty Command Properties 313 14 5 1 Property Definitions 314 14 6 SB File Decryption Support 316 14 6 1 Decryption u...

Page 12: ...features 346 16 1 4 CMP DAC and ANMUX diagram 347 16 1 5 CMP block diagram 348 16 2 Memory map register definitions 350 16 2 1 CMP Control Register 0 CMPx_CR0 350 16 2 2 CMP Control Register 1 CMPx_CR...

Page 13: ...375 17 1 2 Block diagram 375 17 1 3 Modes of operation 376 17 2 Memory map and register descriptions 376 17 2 1 CRC Data register CRC_DATA 377 17 2 2 CRC Polynomial register CRC_GPOLY 378 17 2 3 CRC C...

Page 14: ...eration 394 Chapter 19 Direct Memory Access Multiplexer DMAMUX 19 1 Introduction 395 19 1 1 Overview 395 19 1 2 Features 396 19 1 3 Modes of operation 396 19 2 External signal description 397 19 3 Mem...

Page 15: ...errupt Register DMAx_CEEI 426 20 3 10 Set Enable Error Interrupt Register DMAx_SEEI 427 20 3 11 Clear Enable Request Register DMAx_CERQ 428 20 3 12 Set Enable Request Register DMAx_SERQ 429 20 3 13 Cl...

Page 16: ...Ax_TCDn_CITER_ELINKYES 447 20 3 32 TCD Current Minor Loop Link Major Loop Count Channel Linking Disabled DMAx_TCDn_CITER_ELINKNO 449 20 3 33 TCD Last Destination Address Adjustment Scatter Gather Addr...

Page 17: ...x_DIVISOR 488 21 5 5 Control Register EMVSIMx_CTRL 489 21 5 6 Interrupt Mask Register EMVSIMx_INT_MASK 493 21 5 7 Receiver Threshold Register EMVSIMx_RX_THD 496 21 5 8 Transmitter Threshold Register E...

Page 18: ...rotocol Timers 525 21 6 8 Answer To Reset ATR Detection 528 Chapter 22 Flexible I O FlexIO 22 1 Introduction 533 22 1 1 Overview 533 22 1 2 Features 533 22 1 3 Block Diagram 534 22 1 4 Modes of operat...

Page 19: ...scription 594 23 4 Memory map and register descriptions 594 23 5 Flash Access Control FAC Function 595 23 5 1 Memory map and register definitions 595 23 5 2 FAC functional description 595 23 6 Initial...

Page 20: ...Commands 632 24 4 11 Flash Command Description 633 24 4 12 Security 652 24 4 13 Reset Sequence 655 Chapter 25 Interrupt Multiplexer INTMUX 25 1 About this module 657 25 1 1 Introduction 657 25 1 2 Fe...

Page 21: ...nable 2 register LLWU_PE2 674 26 3 5 LLWU Module Interrupt Enable register LLWU_ME 677 26 3 6 LLWU Module DMA Enable register LLWU_DE 679 26 3 7 LLWU Pin Flag register LLWU_PF 681 26 3 8 LLWU Module I...

Page 22: ...n Register 0 LPI2Cx_MCCR0 713 27 2 13 Master Clock Configuration Register 1 LPI2Cx_MCCR1 714 27 2 14 Master FIFO Control Register LPI2Cx_MFCR 715 27 2 15 Master FIFO Status Register LPI2Cx_MFSR 715 27...

Page 23: ...ter LPITx_VERID 748 28 3 2 Parameter Register LPITx_PARAM 748 28 3 3 Module Control Register LPITx_MCR 749 28 3 4 Module Status Register LPITx_MSR 750 28 3 5 Module Interrupt Enable Register LPITx_MIE...

Page 24: ...e Register LPSPIx_DER 773 29 2 7 Configuration Register 0 LPSPIx_CFGR0 774 29 2 8 Configuration Register 1 LPSPIx_CFGR1 775 29 2 9 Data Match Register 0 LPSPIx_DMR0 777 29 2 10 Data Match Register 1 L...

Page 25: ...er Prescale Register LPTMRx_PSR 799 30 3 3 Low Power Timer Compare Register LPTMRx_CMR 800 30 3 4 Low Power Timer Counter Register LPTMRx_CNR 801 30 4 Functional description 801 30 4 1 LPTMR power and...

Page 26: ...ATCH 829 31 2 10 LPUART Modem IrDA Register LPUARTx_MODIR 829 31 2 11 LPUART FIFO Register LPUARTx_FIFO 832 31 2 12 LPUART Watermark Register LPUARTx_WATER 835 31 3 Functional description 835 31 3 1 B...

Page 27: ...1 Crossbar Switch AXBS Slave Configuration MCMx_PLASC 870 33 2 2 Crossbar Switch AXBS Master Configuration MCMx_PLAMC 871 33 2 3 Platform Control Register MCMx_PLACR 871 33 2 4 Compute Operation Contr...

Page 28: ...mory Descriptor Register MSCM_OCMDRn 887 Chapter 35 Micro Trace Buffer MTB 35 1 Introduction 891 35 1 1 Overview 891 35 1 2 Features 894 35 1 3 Modes of operation 895 35 2 External signal description...

Page 29: ...ge Detect Status And Control 1 register PMC_LVDSC1 982 37 6 4 Low Voltage Detect Status And Control 2 register PMC_LVDSC2 984 37 6 5 Regulator Status And Control register PMC_REGSC 986 37 6 6 High Vol...

Page 30: ...38 6 2 Global pin control 1009 38 6 3 Global interrupt control 1009 38 6 4 External interrupts 1010 38 6 5 Digital filter 1011 Chapter 39 Reset Control Module RCM 39 1 Introduction 1013 39 2 Reset mem...

Page 31: ...36 40 3 1 Port Data Output Register FGPIOx_PDOR 1036 40 3 2 Port Set Output Register FGPIOx_PSOR 1037 40 3 3 Port Clear Output Register FGPIOx_PCOR 1037 40 3 4 Port Toggle Output Register FGPIOx_PTOR...

Page 32: ...ate mode 1053 41 3 6 Register lock 1054 41 3 7 Interrupt 1054 Chapter 42 System Clock Generator SCG 42 1 Introduction 1055 42 1 1 Features 1055 42 2 Memory Map Register Definition 1057 42 2 1 Version...

Page 33: ...2 21 System PLL Configuration Register SCG_SPLLCFG 1087 42 3 Functional description 1089 42 3 1 SCG Clock Mode Transitions 1089 Chapter 43 System Integration Module SIM 43 1 Introduction 1095 43 1 1 F...

Page 34: ...Mode Status register SMC_PMSTAT 1117 44 4 Functional description 1118 44 4 1 Power mode transitions 1118 44 4 2 Power mode entry exit sequencing 1121 44 4 3 Run modes 1123 44 4 4 Wait modes 1125 44 4...

Page 35: ...rol TPMx_CnSC 1147 46 3 9 Channel n Value TPMx_CnV 1149 46 3 10 Combine Channel Register TPMx_COMBINE 1150 46 3 11 Channel Trigger TPMx_TRIG 1152 46 3 12 Channel Polarity TPMx_POL 1153 46 3 13 Filter...

Page 36: ...TRGMUX Register Descriptions 1185 47 2 2 TRGMUX Register Descriptions 1198 Chapter 48 SA TRNG Standalone 48 1 Standalone True Random Number Generator SA TRNG 1211 48 1 1 Standalone True Random Number...

Page 37: ...ference voltage 1278 49 4 8 Current source 1279 49 4 9 End of scan 1279 49 4 10 Out of range interrupt 1279 49 4 11 Wake up MCU from low power modes 1280 49 4 12 DMA function support 1280 49 4 13 Nois...

Page 38: ...51 4 2 Peripheral ID Complement register USBx_IDCOMP 1307 51 4 3 Peripheral Revision register USBx_REV 1308 51 4 4 Peripheral Additional Info register USBx_ADDINFO 1308 51 4 5 OTG Interrupt Status re...

Page 39: ...TRC0 1327 51 4 28 Frame Adjust Register USBx_USBFRMADJUST 1329 51 4 29 Miscellaneous Control register USBx_MISCCTRL 1329 51 4 30 USB Clock recovery control USBx_CLK_RECOVER_CTRL 1330 51 4 31 FIRC osci...

Page 40: ...Functional Description 1352 53 3 1 Voltage Reference Disabled SC VREFEN 0 1352 53 3 2 Voltage Reference Enabled SC VREFEN 1 1352 53 3 3 Internal voltage regulator 1354 53 4 Initialization Application...

Page 41: ...ring the Watchdog Once 1365 54 3 3 Clock source 1367 54 3 4 Using interrupts to delay resets 1368 54 3 5 Backup reset 1368 54 3 6 Functionality in debug and low power modes 1369 54 3 7 Fast testing of...

Page 42: ...K32 L2A Reference Manual Rev 2 01 2020 42 NXP Semiconductors...

Page 43: ...suffixes identify different numbering systems This suffix Identifies a b Binary number For example the binary equivalent of the number 5 is written 101b In some cases binary numbers are shown with the...

Page 44: ...R REVNO 6 4 XAD 7 0 Numbers in brackets and separated by a colon represent either A subset of a register s named field For example REVNO 6 4 refers to bits 6 4 that are part of the COREREV field that...

Page 45: ...uch as USB with crystal less recovery The features of the K32 L2A are Core One Arm Cortex M0 core functional operational up to 96 MHz Memory option is up to 512 KB Flash and 128 KB RAM partitioned to...

Page 46: ...p pins with digital glitch filter and internal wake up sources see LLWU section for details Debug and Trace 2 pin serial wire debug SWD Micro trace buffers MTB Data Watchpoints and Traces DWT Simple C...

Page 47: ...gh current drive ability Single cycle GPIO control via IOPORT Touch sensor inputs TSI 16 channel Selectable Single channel wakeup source available in all modes DMA support Pin interrupt All input Port...

Page 48: ...120 mA Low Power Serial peripheral interface LPSPI0 1 2 3 LPSPIs Functional in Stop VLPS DMA support 4 word FIFO support on all 3 LPSPIs Low Power Inter Integrated Circuit LPI2C0 1 2 3 LPI2C standard...

Page 49: ...sters and 8 Timers 8 16 24 bit smart LCD drive Functional in STOP VLPS modes DMA support 2 4 Block Diagram The below figure shows a top level block diagram of the device Chapter 2 Introduction K32 L2A...

Page 50: ...such as test analog Bus Components Platform Domain Analog Domain Memory protection Gaskets DAP sec exsc S CM0 Platform AHB32 AIPS0 IPBUS AIPS1 IPBUS LEGEND DMA0 8 channel AIPS0 FLASH 1 256KB FLASH 0...

Page 51: ...module chapters Links for more information In more detail The device has 1 CPU also called a core Peripherals attached to the AIPS0 bridge are SoC specific The core and the DMAs have the capability to...

Page 52: ...Count LPTMR0 trigger events LPTMR1_CSR TPS LPTMR0 Hardware trigger to TSI0 TSI triggering TSI0_GENCS STM 3 3 2 Analog reference options Several analog blocks have selectable reference voltages as show...

Page 53: ...g DAP Slave Port Support AHBSLV 1 Supports any AHB debug access port like the CM0 DAP DAP ROM Table Base BASEADDR 0xF000_2003 Base address for DAP ROM table Endianess BE 0 Little endian control for da...

Page 54: ...arm com 3 4 3 Debug facilities This device supports standard Arm 2 pin SWD debug port 3 4 4 Buses interconnects and interfaces The Arm Cortex M0 core has two bus interfaces Single 32 bit AMBA 3 AHB L...

Page 55: ...d NVIC0 vector space INTMUX0 ch0 3 has 4 dedicated vector slots on NVIC0 NVIC1 INTMUX1 Peripheral int Peripheral int NVIC0 INTMUX0 Peripheral int Peripheral int Figure 3 1 Interrupt Routing Block Diag...

Page 56: ...x0000_0018 6 Reserved 0x0000_001C 7 Reserved 0x0000_0020 8 Reserved 0x0000_0024 9 Reserved 0x0000_0028 10 Reserved 0x0000_002C 11 Arm core Supervisor call SVCall 0x0000_0030 12 Reserved 0x0000_0134 13...

Page 57: ...IIC module 1 0x0000_0080 32 16 Reserved 0x0000_0084 33 17 PortA Port A 0x0000_0088 34 18 PortB Port B 0x0000_008C 35 19 PortC Port C 0x0000_0090 36 20 PortD Port D 0x0000_0094 37 21 PortE Port E 0x000...

Page 58: ...eserved 4 LSPI2 5 LPUART2 6 EMVSIM 7 LPI2C2 8 TSI 9 PMC 10 FTFA 11 SCG 12 WDOG0 13 DAC0 14 TRNG 15 RCM 16 CMP0 17 CMP1 18 RTC Alarm 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reser...

Page 59: ...ary function of the AWIC block is to detect asynchronous wake up events in stop modes and then signal to the clock control logic to resume system clocking After the clock restarts the NVIC observes th...

Page 60: ...ng as the module remains clocked LPIT Any enabled interrupt can be a source as long as the module remains clocked FlexIO Any enabled interrupt can be a source as long as the module remains clocked USB...

Page 61: ...sources the device also wakes from low power modes when NMI or RESET pins are enabled and the respective pin is asserted Table 3 8 LLWU Wakeup Sources IRQ Module source or pin name LLWU_P0 PTE1 LLWU_...

Page 62: ...DMAMUX0 is a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 8 DMA channels of DMA0 Because of the mux there is no hard correlation between any of the DMA request...

Page 63: ...mit Yes 19 LPUART2 Receive Yes 20 LPUART2 Transmit Yes 21 LPSPI0 Receive Yes 22 LPSPI0 Transmit Yes 23 LPSPI1 Receive Yes 24 LPSPI1 Transmit Yes 25 LPSPI2 Receive Yes 26 LPSPI2 Transmit Yes 27 TPM0 Ch...

Page 64: ...nverter Yes 55 Reserved 56 CMP0 Comparator Yes 57 CMP1 Comparator Yes 58 Reserved 59 Reserved 60 TSI Touch Sensor Interface Yes 61 LPTMR0 Low Power Timer 0 Yes 62 LPTMR1 Low Power Timer 1 Yes 63 DMA M...

Page 65: ...cludes a 32 byte register file that is powered in all power modes Also it retains contents during low voltage detect LVD events and is only reset during a power on reset Base address of this register...

Page 66: ...k sources that may be asynchronous to the CPU Platform clock SCGIRCLK SCGFIRCLK SCGPCLK SCGFCLK LPO OSCCLK SCGSPCLK 3 5 7 System Register File Configuration This section summarizes how the module has...

Page 67: ...idge 0 slot assignment Security 3 6 1 CAU Configuration There is 1 CAU module CAU0 which is connected to the Core PPB This section summarizes how the module has been configured in the chip For a compr...

Page 68: ...links to related information Topic Related module Reference Full description 16 bit SAR ADC 16 bit SAR ADC System memory map System memory map Clocking Clock distribution Power management Power manag...

Page 69: ...ADC0_SE1 00010 DAD2 ADC0_DP2 and ADC0_DM2 ADC0_DP2 ADC0_SE2 00011 DAD3 ADC0_DP3 and ADC0_DM3 ADC0_DP3 ADC0_SE3 001001 AD4a Reserved ADC0_DM0 ADC0_SE4a 001011 AD5a Reserved ADC0_DM1 ADC0_SE5a 001101 AD...

Page 70: ...uffer by setting the PMC_REGSC BGBE bit Refer to the device data sheet for the bandgap voltage VBG specification 3 7 1 4 ADC analog supply and reference connections See Analog reference options This d...

Page 71: ...erting and non inverting inputs of the comparator Each CMP input channel connects to both muxes Two of the channels are connected to internal sources leaving resources to support up to 6 input pins Se...

Page 72: ...ndgap buffer by setting PMC_REGSC BGBE See the device data sheet for the bandgap voltage VBG specification The following table shows the external output pin options for the CMPs Table 3 15 CMP externa...

Page 73: ...This device includes a voltage reference VREF to supply an accurate 1 2 V or 2 1 V voltage output The voltage reference can provide a reference voltage to external peripherals or a reference to analog...

Page 74: ...n of the module itself see the module s dedicated chapter Signal multiplexing Module signals Register access 12 bit DAC Peripheral bus controller 0 Other peripherals Figure 3 9 12 bit DAC configuratio...

Page 75: ...use of DAC switching Timers 3 8 1 Timer PWM module configuration This section summarizes how the module has been configured in the chip For a comprehensive description of the module itself see the mod...

Page 76: ...t filters dead time insertion and quadrature decode functional in Stop VLPS mode TPM2 2 Basic TPM support for input filters dead time insertion and quadrature decode functional in Stop VLPS mode TPM0...

Page 77: ...nnel 0 or Channel 1 pin input capture 3 8 1 4 TPM interrupts The TPM has multiple sources of interrupt However these sources are OR d together to generate a single interrupt request to the interrupt c...

Page 78: ...clocked from the internal reference clock the internal 1 kHz LPO ERCLK or an external 32 768 kHz crystal In VLLS0 mode the clocking option is limited to an external pin with the OSC configured for by...

Page 79: ...PTMR1_PSR PCS Prescaler glitch filter clock number Chip clock 00 0 SIRCCLK internal reference clock not available in LLS and VLLS modes 01 1 LPO 1 kHz clock not available in VLLS0 mode 10 2 OSC32KCLK...

Page 80: ...h the USB 2 0 specification USB transceiver that includes internal 15 k pulldowns on the D and D lines for host mode functionality and a 1 5 k pullup on the D line for device mode functionality A 3 3...

Page 81: ...powered and self powered USB cases Because the GPIO pins on this device do not directly support a 5V input use an external resistive voltage divider to keep the input voltage within the valid range if...

Page 82: ...ation 3 9 1 2 1 AA AAA cells power supply The chip can be powered by two AA AAA cells In this case the MCU is powered through VDD which is within the 1 8 to 3 0 V range After USB cable insertion is de...

Page 83: ...ttery charger according to the charger detection information USB Regulator USB XCVR USB Controller USB0_DM USB0_DP VDD VOUT33 VREGIN TYPE A D D VBUS Cstab To PMC and Pads Chip VSS Charger Li Ion Si230...

Page 84: ...ty can be used to detect the presence of VBUS in device mode If a GPIO pin with LLWU capability is used VBUS can be detected in all low power modes including LLS and VLLS Software is responsible for d...

Page 85: ...ck Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing NOTE When USB is not used in the application it is recommended that the USB regulator VRE...

Page 86: ...lator VREGIN and VOUT33 pins remain floating 3 9 1 7 USB SRAM In all VLLS power modes USB SRAM is NOT retained but in all the other power modes USB SRAM is retained As a result USB SRAM cannot be used...

Page 87: ...izes how the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Signal multiplexing Register access Peripheral bridge Module...

Page 88: ...dicated chapter Signal multiplexing Register access Peripheral bridge Module signals LPUART Figure 3 20 LPUART configuration Table 3 26 Reference links to related information Topic Related module Refe...

Page 89: ...M Serial Interface Module is a standalone ISO 7816 module that is connected to the AIPS0 Peripheral Bridge The EMVSIM module s clock source is the CPU platform clock 3 9 6 FlexIO This section summariz...

Page 90: ...Register access Peripheral bridge Module signals GPIO controller Arm Cortex M0 Core Register access Figure 3 22 GPIO configuration Table 3 28 Reference links to related information Topic Related modu...

Page 91: ...ORTx_PCRn PE All the pins have controllable pull direction using the PORTx_PCRn PS field All the pins default to pullup except for SWD_CLK when enabled 3 10 1 2 GPIO accessibility in the memory map Th...

Page 92: ...ation This device includes one TSI module containing the channels as shown in the following table In Stop VLPS LLS and VLLSx modes any one channel can be enabled to be the wake up source TSI hardware...

Page 93: ...ription of the module itself see the module s dedicated chapter Register access Signal Multiplexing Port Control Transfers Module Peripheral bus controller 1 Module Module External Pins Transfers Figu...

Page 94: ...aximum of one package pin Do not program the same function to more than one pin 2 To ensure the best signal timing for a given peripheral s interface choose the pins in closest proximity to each other...

Page 95: ...accessed by bus masters through the cross bar switch The amount of System SRAM retained for the different power modes is shown in the following table Table 4 1 System SRAM Retained in Power Modes Pow...

Page 96: ...2D02_0000 0x2D03_FFFF Reserved 0x2D04_0000 0x2D0F_FFFF Reserved 0x2D10_0000 0x2D10_7FFF Reserved 0x2D10_4000 0x2D1F_FFFF Reserved 0x2D20_0000 0x2D21_FFFF Reserved 0x2D22_0000 0x2D23_FFFF Reserved 0x2D...

Page 97: ..._0000 0xEAFF_FFFF 0xEB00_0000 0xEBFF_FFFF 0xEC00_0000 0xEFFF_FFFF Reserved 0xF000_0000 0xF00F_FFFF PPB 0xF010_0000 0xF0FF_FFFF Reserved 0xF100_0000 0xF10F_FFFF Reserved 0xF110_0000 0xF11F_FFFF Reserve...

Page 98: ...gure 4 1 Flash Memory Map 4 5 SRAM Memory Map 1FFF 8000 Physical Address 2001 7FFF 4010 0000 4010 07FF USB SRAM 2 KB SRAM Memory Map Core Core SRAM 128 KB Figure 4 2 SRAM Memory Map 4 6 Bit Manipulati...

Page 99: ...ioned as 96 spaces each 4 KB in size and reserved for off platform modules The AIPS controller generates unique module enables for all 96 spaces Modules that are disabled via their clock gate control...

Page 100: ...01_4000 20 Reserved 0x4001_5000 21 Reserved 0x4001_6000 22 Reserved 0x4001_7000 23 Reserved 0x4001_8000 24 Reserved 0x4001_9000 25 Reserved 0x4001_A000 26 Reserved 0x4001_B000 27 Reserved 0x4001_C000...

Page 101: ...Clock RTC 0x4003_9000 57 Reserved 0x4003_A000 58 Reserved 0x4003_B000 59 Reserved 0x4003_C000 60 Reserved 0x4003_D000 61 Reserved 0x4003_E000 62 LPSPI2 0x4003_F000 63 Reserved 0x4004_0000 64 Reserved...

Page 102: ...multiplex control 0x4005_F000 95 Reserved 0x4006_0000 96 Reserved 0x4006_1000 97 Low leakage Wake up Unit LLWU 0x4006_2000 98 TSI0 0x4006_3000 99 Reserved 0x4006_4000 100 Reserved 0x4006_5000 101 Rese...

Page 103: ...ripheral Slot Assignments AIPS1 System 32 bit base address Slot Source Module 0x4008_0000 0 Reserved 0x4008_1000 1 Reserved 0x4008_2000 2 Reserved 0x4008_3000 3 Reserved 0x4008_4000 4 Reserved 0x4008_...

Page 104: ...d 0x400A_3000 35 Reserved 0x400A_4000 36 Reserved 0x400A_5000 37 Random Number Generator TRNG 0x400A_6000 38 Reserved for Crypto 0x400A_7000 39 TRGMUX 0x400A_8000 40 Reserved 0x400A_9000 41 Reserved 0...

Page 105: ...served 0x400C_7000 71 Reserved 0x400C_8000 72 Reserved 0x400C_9000 73 Reserved 0x400C_A000 74 FlexIO0 0x400C_B000 75 Reserved 0x400C_C000 76 Reserved 0x400C_D000 77 Reserved 0x400C_E000 78 Reserved 0x...

Page 106: ...00 106 Reserved 0x400E_B000 107 Reserved 0x400E_C000 108 Reserved 0x400E_D000 109 Reserved 0x400E_E000 110 Reserved 0x400E_F000 111 CMP1 0x400F_0000 112 Reserved 0x400F_1000 113 Reserved 0x400F_2000 1...

Page 107: ...with the peripheral s registers the second being the peripheral functional clock which is used for the main timing function of the peripheral e g sources the baud rate for a serial communications peri...

Page 108: ...Sources The SCG provides four clock sources that are then distributed and optionally divided to the CPU memory and various peripherals The four clock sources available to the SCG are SOSC output of t...

Page 109: ...for reliable flash operation NOTE Throughout this manual DIVSLOW_CLK may also be referred to as the bus clock 5 3 3 Peripheral functional clocks The SCG provides additional output clock trees that are...

Page 110: ...ck for the USB0 module only It is selectable via the PCCUSB0 register 5 3 3 2 SOSCDIV2_CLK This output clock is fed from the SOSC and is an optional functional clock for peripherals For K32 L2A the SO...

Page 111: ...ptional functional clock for peripherals For K32 L2A the FIRCDIV1_CLK is an optional peripheral functional clock for the USB0 module only It is selectable via the PCCUSB0 register 5 3 3 8 FIRCDIV2_CLK...

Page 112: ...ommunication peripherals It is selectable via the peripherals PCCn register 5 4 Peripheral Clock Summary The SCG module supplies peripheral interface and functional clocks to the PCC depending on the...

Page 113: ...System Mode Controller SMC Chip Reset not VLLS DIVSLOW_CLK Reset Control Module RCM POR LVD VLLS DIVSLOW_CLK LPO Security Integrity WDOG1 Chip Reset DIVSLOW_CLK LPO ERCLK SIRC TRNG Chip Reset DIVSLOW_...

Page 114: ...rom an external pin or from the SCG Internal OSC SOSC and configured with the SCG_SOSCCFG EREFS bit 3 LPTMR clock sources are selected by LPTMR_PSR PCS 4 RTC clock sources are selected by RTC_CR LPOS...

Page 115: ...eral functional clocks This allows the USB0 module to have its functional clock frequency independent of other timer and serial communication peripherals The example below shows the main Peripheral in...

Page 116: ...three different modes of operation normal RUN mode HSRUN mode and Low Power RUN mode Each of these run modes can have different clock sources and dividers options and are automatically selected via th...

Page 117: ..._CLK or DIVCORE_CLK with the peripheral See SCG and PCC chapters for further details 5 8 Other Clock Sources 5 8 1 OSC32KCLK The SCG also provide an additional output from the SOSC named OSC32KCLK whi...

Page 118: ...ck for clocking peripherals tightly coupled with CPU sourced from SPLL Selected via PCCn register of peripheral SOSCDIV3_CLK Alternative clock for clocking low power peripherals sourced from SOSC Sele...

Page 119: ...SIRCDIV3_CLK 8 MHz 8 MHz 8 MHz SCG If not being used by any peripheral and or DIVCORE_CLK OSC32KCLK 30 kHz to 40 kHz 30 40 kHz low range crystal 30 kHz to 40 kHz external crystal oscillator connected...

Page 120: ...prior to changing run modes Once the Core is in normal RUN mode if the HSRUN mode source oscillator is not being used then it can then be disabled Switching from VLPR to HSRUN mode and vice versa is...

Page 121: ...t are needed for their end application The clock to each module will have the capability to be gated on or off via a programmable register Each peripheral has independent clock gating for both the per...

Page 122: ...Flash Memory Clock K32 L2A Reference Manual Rev 2 01 2020 122 NXP Semiconductors...

Page 123: ...Each of the system reset sources has an associated bit in the System Reset Status SRS registers See the Reset Control Module for register details The microcontroller has 1 CPU called the Core By defa...

Page 124: ...t sources Resetting the MCU provides a way to start processing from a known set of initial conditions System reset begins with the on chip regulator in full regulation and system clocking generation f...

Page 125: ...ration or has continued filtering operation depending on the filtering mode selected When entering VLLS0 the RESET pin filter is disabled and bypassed The LPO filter has a fixed filter value of 3 Due...

Page 126: ...akage power modes It also allows for asynchronous DMA wakeup from LLS for certain peripherals The LLWU module is functional only in low leakage power modes In VLLSx modes all enabled inputs to the LLW...

Page 127: ...system reset of all major components except for the debug module A software reset causes RCM_SRS SW to set 6 2 2 9 Lockup reset LOCKUP The LOCKUP gives immediate indication of a seriously errant kerne...

Page 128: ...serts on all reset sources It resets only the flash memory module It negates before flash memory initialization begins earlier than when the Chip Reset negates Chip Reset Chip Reset asserts on all res...

Page 129: ...re core debug registers DHCSR DCRSR DCRDR DEMCR BPU DWT NVIC Crossbar bus switch1 Private peripheral bus1 6 3 Boot The information found here describes the boot sequence including sources and options...

Page 130: ...value of 0x00 is invalid and will be ignored The FOPT register is written to 0xFF if the contents of the Flash nonvolatile option are 0x00 Table 6 3 Flash Option Register FTFA_FOPT definition Bit Num...

Page 131: ...t default to enabled 1 BOOTPIN_OPT External pin selects boot options 0 Force Boot from ROM if BOOTCFG0 asserted where BOOTCFG0 is the boot config function which is muxed with NMI_b pin RESET_b pin mus...

Page 132: ...esulting longer recovery times 5 When flash Initialization completes the RESET pin is released If RESET continues to be asserted an indication of a slow rise time on the RESET pin or external drive in...

Page 133: ...errupt or wake up source it is recommended that the NMI function be disabled by clearing NMI_DIS in the FOPT register Subsequent system resets follow this same reset flow Chapter 6 Reset and Boot K32...

Page 134: ...h init Flash Init Complete RESET released Core clock enabled System released from reset Stack Pointer Program Counter Link Register BOOTPIN_OPT FTFA_FOPT No execution at reset Yes execution at NMI CPU...

Page 135: ...e or VLP Run mode When configured for PSTOP2 only the core and system clocks are gated and the bus clock remains active The bus masters and bus slaves clocked by the system clock enter Stop mode but t...

Page 136: ...and internal power switches enabling the clock generators in the SCG enabling the system and bus clocks but not the core clock and negating the stop mode signal to the bus masters and bus slaves The...

Page 137: ...rate an asynchronous DMA request 7 2 3 Compute Operation Compute Operation is an execution or compute only mode of operation that keeps the CPU enabled with full access to the SRAM and Flash read port...

Page 138: ...module MCM_CPO CPOACK indicates when entry has completed When exiting Compute Operation in Run mode MCM_CPO CPOACK negates immediately When exiting Compute Operation in VLP Run mode the exit is delay...

Page 139: ...ute Operation when executing code and vectors from SRAM 7 2 5 Clock gating To conserve power the clocks to most modules can be turned off using the CGC bit in the PCC module registers For more details...

Page 140: ...als to function while the core is in Sleep mode reducing power NVIC remains sensitive to interrupts Peripherals continue to be clocked Sleep Interrupt STOP Normal Stop via WFI Places chip in static st...

Page 141: ...ks stopped but OSC LLWU LPTMR RTC CMP TSI can be used NVIC is disabled LLWU is used to wake up SRAM_U and SRAM_L remain powered on content retained and I O states held Sleep Deep Wake up Reset 1 VLLS2...

Page 142: ...ode but that is not its intended usage See Arm documentation for more on the WFE instruction On VLLS recoveries the I O pins continue to be held in a static state after code execution begins allowing...

Page 143: ...z LPO FF FF FF FF Optionally OFF controlled by STOPCTRL LPOPO OFF in VLLS0 optionally OFF in VLLS1 2 3 controlled by STOPCTRL LP OPO SCG SYSOSC SIRC enabled SYSOSC SIRC enabled SYSOSC SIRC FIRC SPLL e...

Page 144: ...operation in CPO FF Async operation FF in PSTOP2 Async operation SR OFF LPTMR FF FF Async operation FF in PSTOP2 Async operation Async operation Async operation6 RTC FF Async operation in CPO FF Async...

Page 145: ...uires the function controlling the pin GPIO or peripheral to be configured as an input to allow a transition to occur to the LLWU 2 When LPO clock source is disabled filters will be bypassed 3 STOPCTR...

Page 146: ...Module operation in low power modes K32 L2A Reference Manual Rev 2 01 2020 146 NXP Semiconductors...

Page 147: ...Debug security Debug enables access to the Core for debugging and also for programming the flash arrays For the standard Programming mechanism you make use of the FTFx_SEC register to enable security...

Page 148: ...e security byte of the flash configuration field NOTE The security features apply only to external accesses debug CPU accesses to the flash are not affected by the status of FTFA_FSEC In the unsecured...

Page 149: ...rovide simple program trace Only one debug interface is supported Serial Wire Debug SWD The SWD interface provides the capability for debugger tools to interface to the CPU 9 2 Debug port pin descript...

Page 150: ...SWD_DIO SWD_CLK Figure 9 1 Debug and Trace Block Diagram Details The Debug and Trace uses these Arm based modules DP AHB AP DBG MTB MTBDWT and CTI The device has 1 Arm based Debug Port DP that suppor...

Page 151: ...hown in the figure found here These registers provide additional control and status for low power mode recovery and typical run control scenarios The status register bits also provide a means for the...

Page 152: ...ister Table 9 4 MDM AP Control register assignments Bit Name Secure1 Description 0 Flash Mass Erase in Progress Y Set to cause mass erase Cleared by a Power On Reset POR When mass erase is disabled vi...

Page 153: ...e exited to allow the debugger time to re initialize debug IP before the debug session continues The Mode Controller captures VLLSx Debug Request bit logic on entry to VLLSx modes Upon exit from VLLSx...

Page 154: ...S or VLLSx are the selected power mode for the next time that the Arm Core enters Deep Sleep 0 Low Power Stop Mode is not enabled 1 Low Power Stop Mode is enabled This bit is intended to be used for d...

Page 155: ...17 CPU0 Core SLEEPDEEP Indicates the CPU0 core has entered a low power mode SLEEPING 1 and SLEEPDEEP 0 indicates wait or VLPW mode SLEEPING 1 and SLEEPDEEP 1 indicates stop or VLPS mode 18 CPU0 Core S...

Page 156: ...ace The MTB includes trace control registers for configuring and triggering the MTB functions The MTB also supports triggering via TSTART and TSTOP control functions in the MTB DWT module 9 7 Debug in...

Page 157: ...the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation 9 8 Debug and security When flash security...

Page 158: ...Debug and security K32 L2A Reference Manual Rev 2 01 2020 158 NXP Semiconductors...

Page 159: ...ntrols the operation of a specific pin For more information about how the Port Control block is integrated into this device refer to the Signal multiplexing integration section Pinout 10 2 1 Package t...

Page 160: ...g filter disabled after POR SWD_DIO pin has pullup device enabled after POR SWD_CLK has pulldown device enabled after POR 100 LQFP 64 LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 1 1...

Page 161: ...MP1_IN5 CMP0_IN5 ADC0_SE4b CMP1_IN5 CMP0_IN5 ADC0_SE4b PTE29 EMVSIM0_CLK TPM0_CH2 TPM0_CLKIN 27 18 PTE30 DAC0_OUT CMP1_IN3 ADC0_SE23 CMP0_IN4 DAC0_OUT CMP1_IN3 ADC0_SE23 CMP0_IN4 PTE30 EMVSIM0_ RST TP...

Page 162: ...CH8 PTB3 LPI2C0_SDA TPM2_CH1 LPSPI1_PCS3 LPUART0_ CTS_b FXIO0_D11 57 PTB7 DISABLED PTB7 LPSPI1_PCS1 58 PTB8 DISABLED PTB8 LPSPI1_PCS0 FXIO0_D12 59 PTB9 DISABLED PTB9 LPSPI1_SCK FXIO0_D13 60 PTB10 DISA...

Page 163: ...TPM1_CLKIN 86 PTC14 DISABLED PTC14 EMVSIM0_CLK 87 PTC15 DISABLED PTC15 EMVSIM0_ RST 88 VSS VSS VSS 89 VDD VDD VDD 90 PTC16 DISABLED PTC16 EMVSIM0_ VCCEN 91 PTC17 DISABLED PTC17 EMVSIM0_IO LPSPI0_PCS3...

Page 164: ...inout diagram for the devices supported by this document Many signals may be multiplexed onto a single pin To determine what signals can be used on which pin see the previous section Pinout K32 L2A Re...

Page 165: ...REF_OUT VDDA PTE23 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 PTD6 LLWU_P15 PTC7 PTC6 LLWU_P10 PTC5 LLWU_P9 PTC4 LLWU_P8 50 49 48 47 46 45 44 43 42 41 PTA18 VSS VDD PTA17 PTA16 PTA15...

Page 166: ...1 PTD7 PTD6 LLWU_P15 PTD5 PTD4 LLWU_P14 PTD3 PTD2 LLWU_P13 PTD1 PTD0 LLWU_P12 PTC11 LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6 LLWU_P10 PTC5 LLWU_P9 PTC4 LLWU_P8 VDD VSS PTC3 LLWU_P7 PTC2 PTC1 LLWU_P6 PTC0 PT...

Page 167: ...Description I O NMI0_b Non maskable interrupt Driving the NMI0_b signal low forces a non maskable interrupt if the NMI function is selected on the corresponding pin NOTE If the NMI function is not re...

Page 168: ...ule Table 10 5 CMP0 signal descriptions Chip signal name Module signal name Description I O CMP0_IN 5 0 IN 5 0 Analog voltage inputs I CMP0_OUT CMPO Comparator output O This table presents the signal...

Page 169: ...in is an input I O Table 10 9 TPM2 signal descriptions Chip signal name Module signal name Description I O TPM2_CLKIN TPM_EXTCLK External clock TPM external clock can be selected to increment the TPM...

Page 170: ...r mode I O LPSPI0_PCS 0 PCS 0 Peripheral Chip Select Input in slave mode output in master mode I O LPSPI0_PCS 1 PCS 1 HREQ Peripheral Chip Select or Host Request Host Request pin is selected when HREN...

Page 171: ...I O LPSPI2_SCK SCK Serial clock Input in slave mode output in master mode I O LPSPI2_PCS 0 PCS 0 Peripheral Chip Select Input in slave mode output in master mode I O LPSPI2_PCS 1 PCS 1 HREQ Periphera...

Page 172: ...Secondary I2C data line In 4 wire mode this is the SDA output pin If LPI2C master slave are configured to use separate pins then this is the LPI2C slave SDA pin I O Table 10 19 LPI2C2 signal descript...

Page 173: ...cription I O PTA 31 0 1 PORTA31 PORTA0 General purpose input output I O PTB 31 0 1 PORTB31 PORTB0 General purpose input output I O PTC 31 0 1 PORTC31 PORTC0 General purpose input output I O PTD 31 0 1...

Page 174: ...Module Signal Description Tables K32 L2A Reference Manual Rev 2 01 2020 174 NXP Semiconductors...

Page 175: ...Features Following are the features of the ADC module Linear successive approximation algorithm with up to 16 bit resolution Up to four pairs of differential and 24 single ended external analog inputs...

Page 176: ...ource for lower noise operation with option to output the clock Selectable hardware conversion trigger with hardware channel select Automatic compare with interrupt for less than greater than or equal...

Page 177: ...AVGS ADCOFS V REFSH V REFSL SC2 CFG1 CFG2 Conversion trigger control Clock divide Control sequencer Bus clock SAR converter Compare logic Offset subtractor Averager Formatting ADLSMP ADLSTS ADLPC ADH...

Page 178: ...tential as VDD External filtering may be necessary to ensure clean VDDA for good results 11 2 2 Analog Ground VSSA The ADC analog portion uses VSSA as its ground connection In some packages VSSA is co...

Page 179: ...s DADPx and DADMx referenced to each other to provide the most accurate analog to digital readings A differential input is selected for conversion through SC1 ADCH when SC1n DIFF is high All DADPx inp...

Page 180: ...er ADC0_CLP3 32 R W 0000_0100h 11 3 14 196 4006_6044 ADC Plus Side General Calibration Value Register ADC0_CLP2 32 R W 0000_0080h 11 3 15 196 4006_6048 ADC Plus Side General Calibration Value Register...

Page 181: ...MCU Writing SC1A while SC1A is actively controlling a conversion aborts the current conversion In Software Trigger mode when SC2 ADTRG 0 writes to SC1A subsequently initiate a new conversion if SC1 AD...

Page 182: ...Input channel select Selects one of the input channels The input channel decode depends on the value of DIFF DAD0 DAD3 are associated with the input pin pairs DADPx and DADMx NOTE Some of the input c...

Page 183: ...When DIFF 0 AD19 is selected as input when DIFF 1 it is reserved 10100 When DIFF 0 AD20 is selected as input when DIFF 1 it is reserved 10101 When DIFF 0 AD21 is selected as input when DIFF 1 it is re...

Page 184: ...ced at the expense of maximum clock speed 6 5 ADIV Clock Divide Select Selects the divide ratio used by the ADC to generate the internal clock ADCK 00 The divide ratio is 1 and the clock rate is input...

Page 185: ...uired to be active prior to conversion start When it is selected and it is not active prior to a conversion start when CFG2 ADACKEN 0 the asynchronous clock is activated at the start of a conversion a...

Page 186: ...High Speed Configuration Configures the ADC for very high speed operation The conversion sequence is altered with 2 ADCK cycles added to the conversion time to allow higher speed conversion clocks 0 N...

Page 187: ...ement 12 bit single ended 0 0 0 0 D D D D D D D D D D D D Unsigned right justified 11 bit differential S S S S S S D D D D D D D D D D Sign extended 2 s complement 10 bit single ended 0 0 0 0 0 0 D D...

Page 188: ...ds that are related to the ADC mode of operation The compare value 2 register CV2 is used only when the compare range function is enabled that is SC2 ACREN 1 Address 4006_6000h base 18h offset 4d i wh...

Page 189: ...0 0 0 0 0 0 0 ADCx_SC2 field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 ADACT Conversion Active Indicates that a...

Page 190: ...ve functionality based on the values placed in CV1 and CV2 3 ACREN Compare Function Range Enable Configures the compare function to check if the conversion result of the input being monitored is eithe...

Page 191: ...ys set while the calibration is in progress and is cleared when the calibration sequence is completed CALF must be checked to determine the result of the calibration sequence Once started the calibrat...

Page 192: ...1 8 samples averaged 10 16 samples averaged 11 32 samples averaged 11 3 8 ADC Offset Correction Register ADCx_OFS The ADC Offset Correction Register OFS contains the user selected or calibration gener...

Page 193: ...Address 4006_6000h base 2Ch offset 4006_602Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0...

Page 194: ...calibration values of varying widths CLP0 5 0 CLP1 6 0 CLP2 7 0 CLP3 8 0 CLP4 9 0 CLPS 5 0 and CLPD 5 0 CLPx are automatically set when the self calibration sequence is done that is CAL is cleared If...

Page 195: ...lue 0 CLPS Calibration Value Calibration Value 11 3 13 ADC Plus Side General Calibration Value Register ADCx_CLP4 For more information see CLPD register description Address 4006_6000h base 3Ch offset...

Page 196: ...e value 0 CLP3 Calibration Value Calibration Value 11 3 15 ADC Plus Side General Calibration Value Register ADCx_CLP2 For more information see CLPD register description Address 4006_6000h base 44h off...

Page 197: ...alue 0 CLP1 Calibration Value Calibration Value 11 3 17 ADC Plus Side General Calibration Value Register ADCx_CLP0 For more information see CLPD register description Address 4006_6000h base 4Ch offset...

Page 198: ...tion Address 4006_6000h base 54h offset 4006_6054h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CLMD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 199: ...ption 31 10 Reserved This field is reserved This read only field is reserved and always has the value 0 CLM4 Calibration Value Calibration Value 11 3 21 ADC Minus Side General Calibration Value Regist...

Page 200: ...his read only field is reserved and always has the value 0 CLM2 Calibration Value Calibration Value 11 3 23 ADC Minus Side General Calibration Value Register ADCx_CLM1 For more information see CLMD re...

Page 201: ...ronous clock output enable is disabled or CFG2 ADACKEN 0 the module is in its lowest power state The ADC can perform an analog to digital conversion on any of the software selectable channels All mode...

Page 202: ...from a clock source within the ADC module When the ADACK clock source is selected it is not required to be active prior to conversion start When it is selected and it is not active prior to a convers...

Page 203: ...urce is available and hardware trigger is enabled that is SC2 ADTRG 1 a conversion is initiated on the rising edge of ADHWT after a hardware trigger select event that is ADHWTSn has occurred If a conv...

Page 204: ...rmined by CFG1 MODE and SC1n DIFF as shown in the description of CFG1 MODE Conversions can be initiated by a software or hardware trigger In addition the ADC module can be configured for Low power ope...

Page 205: ...re triggered operation conversions begin after SC1A is written In hardware triggered operation conversions begin after a hardware trigger If continuous conversions are also enabled a new set of conver...

Page 206: ...Normal Stop mode with ADACK or Alternate Clock Sources not enabled When a conversion is aborted the contents of the data registers Rn are not altered The data registers continue to be the values tran...

Page 207: ...speed configuration that is CFG2 ADHSC The frequency of the conversion clock that is fADCK CFG2 ADHSC is used to configure a higher clock input frequency This will allow faster overall conversion tim...

Page 208: ...s time adder SFCAdder 1 x 0x 10 3 ADCK cycles 5 bus clock cycles 1 1 11 3 ADCK cycles 5 bus clock cycles1 1 0 11 5 s 3 ADCK cycles 5 bus clock cycles 0 x 0x 10 5 ADCK cycles 5 bus clock cycles 0 1 11...

Page 209: ...s 1 2 ADCK cycles Note The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications 11 4 4 6 Conversion time examples The following examples use the Equation 1 on page...

Page 210: ...e configuration A configuration for long ADC conversion is 16 bit differential mode with the bus clock selected as the input clock source The input clock divide by 8 ratio selected Bus frequency of 8...

Page 211: ...er 5 ADCK cycles 5 bus clock cycles AverageNum 1 BCT 17 ADCK cycles LSTAdder 0 ADCK cycles HSCAdder 2 The resulting conversion time is generated using the parameters listed in in the preceding table T...

Page 212: ...After the input is sampled and converted the compare values in CV1 and CV2 are used as described in the following table There are six Compare modes as shown in the following table Table 11 11 Compare...

Page 213: ...hannel while the MCU is in Wait or Normal Stop modes The ADC interrupt wakes the MCU when the compare condition is met 11 4 6 Calibration function The ADC contains a self calibration function that is...

Page 214: ...AL to clear and SC3 CALF to set At the end of a calibration sequence SC1n COCO will be set SC1n AIEN can be used to allow an interrupt to occur at the end of a calibration sequence At the end of the c...

Page 215: ...rrent mode of operation The formatting of the OFS is different from the data result register Rn to preserve the resolution of the calibration value regardless of the conversion mode selected Lower ord...

Page 216: ...d to the user defined offset For applications that may change the offset repeatedly during operation store the initial offset calibration value in flash so it can be recovered and added to any user of...

Page 217: ...and ADACK are available as conversion clock sources while in Wait mode The use of ALTCLK as the conversion clock source in Wait is dependent on the definition of ALTCLK for this MCU See the Chip Conf...

Page 218: ...he respective ADC interrupt is enabled that is when SC1n AIEN 1 The result register Rn will contain the data from the first completed conversion that occurred during Normal Stop mode If the hardware a...

Page 219: ...ntinuous or completed only once ADCO and whether to perform hardware averaging 5 Update SC1 SC1n registers to select whether conversions will be single ended or differential and to enable or disable c...

Page 220: ...001 Bit 7 COCO 0 Read only flag which is set when a conversion completes Bit 6 AIEN 1 Conversion complete interrupt enabled Bit 5 DIFF 0 Single ended conversion selected Bit 4 0 ADCH 00001 Input chann...

Page 221: ...s In these cases there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained If separ...

Page 222: ...itor with good high frequency characteristics This capacitor is connected between VREFH and VREFL and must be placed as near as possible to the package pins Resistance in the path is not recommended b...

Page 223: ...rror in LSBs N 8 in 8 bit mode 10 in 10 bit mode 12 in 12 bit mode or 16 in 16 bit mode Higher source resistances or higher accuracy sampling is possible by setting CFG1 ADLSMP and changing CFG2 ADLST...

Page 224: ...Normal Stop reduces VDD noise but increases effective conversion time due to stop recovery There is no I O switching input or output on the MCU during the conversion There are some situations where e...

Page 225: ...the quantization error is 1 LSB to 0 LSB and the code width of each step is 1 LSB 11 6 2 5 Linearity errors The ADC may also exhibit non linearity of several forms Every effort has been made to reduc...

Page 226: ...ues when sampled repeatedly Ideally when the input voltage is infinitesimally smaller than the transition voltage the converter yields the lower code and vice versa However even small amounts of syste...

Page 227: ...tructure This structure allows up to four bus masters to access different bus slaves simultaneously while providing arbitration among the bus masters when they access the same slave 12 1 1 Features Th...

Page 228: ...vice the master device has no knowledge of whether it actually owns the slave port it is targeting While the master does not have control of the slave port it is targeting it simply waits After the ma...

Page 229: ...ble of addressing 512 KB of peripheral address space BME2 supports an 8 bit or less data field width for bit field inserts and extracts regardless of reference size All other BME2 operations are exact...

Page 230: ...ations Decorated stores support bit field inserts logical AND OR and XOR operations Support for byte halfword and word sized decorated operations Supports minimum signal toggling on AHB output bus to...

Page 231: ...e addressing in the Embedded C standard For most BME commands a single core read or write bus cycle is converted into an atomic read modify write that is an indivisible read followed by a write bus se...

Page 232: ...from input bus is translated into a read operation on the output bus using the actual memory address with the decoration removed and then captured in a register 2 Cycle x 1 2nd AHB address phase Write...

Page 233: ...peration and mem_addr 19 0 specifies the address offset into the space based at a 0x4000_0000 for peripherals The indicates an address bit don t care The decorated AND write operation is defined in th...

Page 234: ...ord 32 bit The core performs the required write data lane replication on byte and halfword transfers ioorb 0 0 0 1 mem_addr ioorh 0 0 0 1 mem_addr ioorw 0 0 0 1 mem_addr 0 1 2 3 4 5 6 7 8 9 10 11 12 1...

Page 235: ...and can be byte 8 bit halfword 16 bit or word 32 bit The core performs the required write data lane replication on byte and halfword transfers ioxorb 0 0 1 mem_addr ioxorh 0 0 1 mem_addr ioxorw 0 0 1...

Page 236: ...width addr 22 20 for bit field inserts and extracts is limited to an 8 bit or less value regardless of reference size NOTE The maximum bit field width is 8 bits The core performs the required write da...

Page 237: ...gister 7 0 xy_z then destination is abxy_zfgh if b 4 and the decorated store strb Rt register 7 0 xyz_ then destination is axyz_efgh if b 5 and the decorated store strb Rt register 7 0 xyz _ then dest...

Page 238: ...is performed in the second AHB data phase as the original read data is returned to the processor core For an unsigned bit field extract the decorated load transaction is stalled for one cycle in the...

Page 239: ...bus is translated into a read operation on the output bus with the actual memory address with the decoration removed and then captured in a register 2 Cycle x 1 second AHB address phase Write access...

Page 240: ...rdata 5 v_wxyz next rdata Figure 13 7 Decorated load unsigned bit field insert timing diagram The decorated unsigned bit field extract follows the same execution template shown in the above figure a 2...

Page 241: ...operand returned to the core The data size is specified by the read operation and can be byte 8 bit halfword 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...

Page 242: ...d modify write sequence The extracted one bit data field from the memory address is right justified and zero filled in the operand returned to the core The data size is specified by the read operation...

Page 243: ...b and the bit field width w 1 from the memory container defined by the access size associated with the load instruction using a two cycle read sequence The extracted bit field from the memory address...

Page 244: ...The cycle by cycle BME operations are detailed in the following table Table 13 7 Cycle definitions of decorated load unsigned bit field extract Pipeline Stage Cycle x x 1 x 2 BME AHB_ap Forward addr t...

Page 245: ...r3 1 27 orr r3 addr mov r2 wdata strh r2 r3 addr r ADDR wdata r WDATA r2 r3 define IOORB ADDR WDATA __asm ldr r3 1 27 orr r3 addr mov r2 wdata strb r2 r3 addr r ADDR wdata r WDATA r2 r3 define IOXORW...

Page 246: ...Application information K32 L2A Reference Manual Rev 2 01 2020 246 NXP Semiconductors...

Page 247: ...0xFF bytes then all peripherals will be enabled by default The next table shows the pads used by the Kinetis ROM Bootloader Table 14 1 Kinetis Bootloader Peripheral Pinmux Peripheral Instance Alt Mod...

Page 248: ...execution of the Kinetis Bootloader from on chip ROM The Kinetis Bootloader s main task is to provision the internal flash memory with an embedded firmware image during manufacturing or at any time d...

Page 249: ...n options Fully supports internal flash security including ability to mass erase or unlock security via the backdoor key Protection of RAM used by the bootloader while it is running Provides command t...

Page 250: ...unlock flash security using the backdoor key Supported GetProperty Get the current value of a property Supported ReceiveSbFile Receive an SB file which is generated by the elftosb tool Supported if th...

Page 251: ...e bootloader Table 14 3 Configuration Fields for the Kinetis Bootloader Offset Size bytes Configuration Field Description 0x00 0x03 4 tag Magic number to verify bootloader configuration is valid Must...

Page 252: ...orted by the device during enumeration Default string values are described in the USB peripheral section 0x1C 1 clockFlags See Table 14 5 clockFlags Configuration Field 0x1D 1 clockDivider Inverted va...

Page 253: ...are to start the Kinetis Bootloader FOPT 7 is set to 1 This forces the ROM to run out of reset The BOOTCFG0 pin is asserted The pin must be configured as BOOTCFG0 by setting the BOOTPIN_OPT bit of FOP...

Page 254: ...was all 0xFF bytes 4 Clocks are configured See the Clock Configuration section 5 If BOOTSRC_SEL is set to 0b10 then the QSPI0 interface is configured by reading the configuration block from the base a...

Page 255: ...nused Peripherals Jump to user application Enter bootloader state machine No Yes No No No Yes No Yes Yes Yes Was a activity detected on USB No Was Yes No Is direct boot valid No Yes Init flash USB LPI...

Page 256: ...the bus clock frequency is at or below the maximum Note that the maximum baud rate of serial peripherals is related to the core and bus clock frequencies To achieve the desired baud rates high speed...

Page 257: ...ROM API tree runBootloaderAddress uint32_t 0x1c00001c runBootloader void void arg runBootloaderAddress Start the bootloader runBootloader NULL 14 3 6 Bootloader Protocol This section explains the gen...

Page 258: ...has processed 14 3 6 1 Command with no data phase The protocol for a command with no data phase contains Command packet from host Generic response command packet to host Command Host Target ACK Proce...

Page 259: ...urther packets while it the host is waiting for the response to a command If the Generic Response packet prior to the start of the data phase does not have a status of kStatus_Success then the data ph...

Page 260: ...r the entire operation 14 3 6 3 Command with outgoing data phase The protocol for a command with an outgoing data phase contains Command packet from host ReadMemory Response command packet to host kCo...

Page 261: ...above the data phase is really considered part of the response command The host may not send any further packets while it the host is waiting for the response to a command If the ReadMemory Response...

Page 262: ...a communication between host and target is packetized NOTE The term target refers to the Kinetis Bootloader device There are 6 types of packets used in the device Ping packet Ping Response packet Fram...

Page 263: ...coming Ping packet to determine the baud rate before replying with the Ping Response packet Once the Ping Response packet is received by the host the connection is established and the host starts send...

Page 264: ...s See the CRC16 algorithm after this table 5 crc16_high 6 n Command or Data packet payload A special framing packet that contains only a start byte and a packet type is used for synchronization betwee...

Page 265: ...o Ping contains the framing protocol version number and options CRC16 algorithm uint16_t crc16_update const uint8_t src uint32_t lengthInBytes uint32_t crc 0 uint32_t j for j 0 j lengthInBytes j uint3...

Page 266: ...r is followed by 32 bit parameters up to the value of the ParameterCount field specified in the header Because a command packet is 32 bytes long only 7 parameters can fit into the command packet Comma...

Page 267: ...s that will be transferred in the data phase is determined by a command specific parameter in the parameters array ParameterCount The number of parameters included in the command packet Parameters The...

Page 268: ...The Status codes are errors encountered during the execution of a command by the target Kinetis Bootloader If a command succeeds then a kStatus_Success code is returned Table 14 62 Kinetis Bootloader...

Page 269: ...arameters Byte Parameter Descripton 0 3 Status code The status of the associated Read Memory command 4 7 Data byte count The number of bytes sent in the data phase FlashReadOnceResponse The FlashReadO...

Page 270: ...is Bootloader in ROM see Table 14 62 Kinetis Bootloader Status Error Codes NOTE All the examples in this section depict byte traffic on serial peripherals that use framing packets USB HID transactions...

Page 271: ...to kStatus_InvalidArgument 105 14 3 8 2 ReceiveSBFile command The ReceiveSBFile command ReceiveSbFile will start the transfer of an SB file to the target The command only specifies the size in bytes...

Page 272: ...s function argument pointer and stack pointer are the parameters required for the Execute command Table 14 22 Parameters for Execute Command Byte Command 0 3 Jump address 4 7 Argument word 8 11 Stack...

Page 273: ...00 The Reset command has no data phase Response The target Kinetis Bootloader will return a GenericResponse packet with status code set to kStatus_Success before resetting the chip 14 3 8 5 GetPropert...

Page 274: ...Command Byte Command 0 3 Property tag Host Target Process Command Generic Response ACK 0x5A A1 ACK 0x5A A1 0x5A A4 0C 00 07 7A A7 00 00 02 00 00 00 00 00 00 01 4B 0x5A A4 08 00 73 D4 07 00 00 01 01 0...

Page 275: ...cket responseTag 0xA7 flags 0x00 reserved 0x00 parameterCount 0x02 status 0x00000000 propertyValue 0x0000014b CurrentVersion 14 3 8 6 SetProperty command The SetProperty command is used to change or a...

Page 276: ...kFramingPacketType_Command length 0x0C 0x00 crc16 0x67 0x8D Command packet commandTag 0x0C SetProperty with property tag 10 flags 0x00 reserved 0x00 parameterCount 0x02 propertyTag 0x0000000A VerifyWr...

Page 277: ...Tag field of the command packet The FlashEraseAll command requires no parameters Host Target Process Command ACK 0x5A A1 ACK 0x5A A1 0x5A A4 04 00 C4 2E 01 00 00 00 0x5A A4 0C 00 53 63 A0 00 04 02 00...

Page 278: ...ion command will fail and return kStatus_FlashAlignmentError 0x101 If the region specified does not fit in the flash memory space the FlashEraseRegion command will fail and return kStatus_FlashAddress...

Page 279: ...se Status Codes Status Code kStatus_Success 0x0 kStatus_MemoryRangeInvalid 0x10200 kStatus_FlashAlignmentError 0x101 kStatus_FlashAddressError 0x102 kStatus_FlashAccessError 0x103 kStatus_FlashProtect...

Page 280: ...ket commandTag 0x0D FlashEraseAllUnsecure flags 0x00 reserved 0x00 parameterCount 0x00 The FlashEraseAllUnsecure command has no data phase Response The target Kinetis Bootloader will return a GenericR...

Page 281: ...1 ACK 0x5A A1 Generic Response FlashProgramOnce index 0 byteCount 4 data 0x12345678 0x5A A4 10 00 7E 89 0E 00 00 03 00 00 00 00 04 00 00 00 78 56 34 12 0x5A A4 0C 00 88 1A A0 00 00 02 00 00 00 00 0E 0...

Page 282: ...en index and byte count The FlashReadOnce command uses 2 parameters index and byteCount Table 14 37 Parameters for FlashReadOnce Command Byte Parameter Description 0 3 index Index of the program once...

Page 283: ...0000 byteCount 0x0000_0004 data 0x1234_5678 Response upon successful execution of the command the target Kinetis Bootloader will return a FlashReadOnceResponse packet with a status code set to kStatus...

Page 284: ...0x5A A4 0C 00 08 D2 B0 01 00 02 00 00 00 00 08 00 00 00 0x5A A4 10 00 B3 CC 10 00 00 03 00 00 00 00 08 00 00 00 01 00 00 00 FlashReadResource startAddress 0 byteCount 8 option 1 FlashReadResource Res...

Page 285: ...ootloader works in slave mode the host must pull data packets until the number of bytes of data specified in the byteCount parameter of FlashReadResource command are received by the host 14 3 8 13 Fla...

Page 286: ...col Sequence for FlashSecurityDisable Command Table 14 44 FlashSecurityDisable Command Packet Format Example FlashSecurityDisable Parameter Value Framing packet start byte 0x5A packetType 0xA4 kFramin...

Page 287: ...umber of bytes must be evenly divisible by 4 8 11 32 bit pattern To fill with a byte pattern 8 bit the byte must be replicated 4 times in the 32 bit pattern To fill with a short pattern 16 bit the sho...

Page 288: ...ommandTag 0x05 FillMemory flags 0x00 Reserved 0x00 parameterCount 0x03 startAddress 0x00007000 byteCount 0x00000800 patternWord 0x12345678 The FillMemory command has no data phase Response upon succes...

Page 289: ...ed with the flash erase pattern 0xff If the VerifyWrites property is set to true then writes to flash will also perform a flash verify program operation When writing to RAM the start address need not...

Page 290: ...CK 0x5A A1 WriteMemory startAddress 0x20000400 byteCount 0x64 Process Command Process Data Process Data Figure 14 19 Protocol Sequence for WriteMemory Command Table 14 48 WriteMemory Command Packet Fo...

Page 291: ...emory command The ReadMemory command returns the contents of memory at the given address for a specified number of bytes This command can read any region of Flash memory SRAM_L and SRAM_U memory acces...

Page 292: ...23 03 00 00 02 00 04 00 20 64 00 00 00 Final Generic Response 0x5A A4 0C 00 0E 23 A0 00 00 02 00 00 00 00 03 00 00 00 Figure 14 20 Command sequence for ReadMemory Table 14 50 ReadMemory Command Packe...

Page 293: ...ate The Kinetis Bootloader tries to reconfigure the system back to the reset state in the following situations After completion of an Execute command but before jumping to the specified entry point Af...

Page 294: ...slave address The maximum supported LPI2C baud rate depends on corresponding clock configuration field in the BCA Typical supported baud rate is 400 kbps with factory settings Actual supported baud ra...

Page 295: ...ping response from target via LPI2C Fetch ACK No Yes End No Process NAK Yes Report an error No Yes No Reached maximum retries Report a timeout error Yes 0x5A received 0xA2 received 0xA1 received Read...

Page 296: ...A shown in Table 14 3 The typical supported baud rate is 400 kbps with the factory settings The actual baud rate is lower or higher than 400 kbps depending on the actual value of the clockFlags and cl...

Page 297: ...ckets to identify real data and not dummy 0x00 bytes which do not have framing packets The following flowcharts demonstrate how the host reads a ping response an ACK and a command response from target...

Page 298: ...arget 2 bytes out CRC checksum from target Payload length less than supported length Yes out payload data from target No Set payload length to maximum supported length No No maximum Report a timeout e...

Page 299: ...the QuadSPI all unused QuadSPI configuration fields should be set to 0 Table 14 52 Configuration fields in QSPI config block Offset Size bytes Configuration Field Description 0x00 0x03 4 tag A magic n...

Page 300: ...PI0B_CS0 in bytes sflash_B1_size field must be set to 0 if the serial flash device is not present 0x40 0x43 4 sflash_B2_size Size of external flash connected to ports of QSPI0B and quadSPI0B_CS1 in by...

Page 301: ...PI0B_CS1 is enabled portB_cs1 field must be set to 1 if sflash_B2_size is not equal to 0 0x68 0x6b 4 fsphs Full Speed Phase selection for SDR instructions 0 Select sampling at non inverted clock 1 Sel...

Page 302: ...ncy Enable 0 DQS latency disabled 1 DQS feature with latency included enabled 0x1ac 0x1af 4 dqs_loopback_internal DQS loopback from internal DQS signal or DQS Pad 0 DQS loopback is sent to DQS pad fir...

Page 303: ...EraseAll Sequence for EraseAll instructions 3 ReadStatus Sequence for ReadStatus instructions 4 PageProgram Sequence for Page Program instructions 6 PreErase1 Sequence for Pre Erase instructions 7 Sec...

Page 304: ...RC48M QUADSPI0_SOCCR QSPISRC equals 4 start up The steps of configuring QuadSPI at startup is based on the runtime procedure if the QCB is not present at address 0 of the 1st external SPI flash device...

Page 305: ...ng down the QSPI clock during clock switching for example if the clock switch related codes are relocated in either internal flash or SRAM Table 14 55 Register value updates when the QuadSPI module is...

Page 306: ...piFlashAlignmentError 401 Start Address for program is not page aligned kStatus_QspiFlashAddressError 402 The address is invalid kStatus_QspiFlashCommandFailure 403 The operation failed kStatus_QspiNo...

Page 307: ...l be ignored as noise The data bytes of the ping packet must be sent continuously with no more than 80 ms between bytes in a fixed LPUART transmission mode 8 bit data no parity bit and 1 stop bit If t...

Page 308: ...target retries Figure 14 27 Host reads an ACK from target via LPUART Wait for ping response Yes Yes End Report Error No No Wait for 1 byte from target Wait for 1 byte from target 0x5A received 0xA7 re...

Page 309: ...et is implemented as a USB HID class USB HID does not use framing packets instead the packetization inherent in the USB protocol itself is used The ability for the device to NAK Out transfers until th...

Page 310: ...ringsPointer BCA 0x18 field of the BCA g_languages USB_STR_0 sizeof USB_STR_0 uint_16 0x0409 const uint_8 g_string_descriptors g_string_desc_size the USB_STR_0 g_string_descriptors and g_string_desc_s...

Page 311: ..._STRING_DESCRIPTOR U 0 S 0 B 0 0 C 0 O 0 M 0 P 0 O 0 S 0 I 0 T 0 E 0 0 D 0 E 0 V 0 I 0 C 0 E 0 USB_STR_3 sizeof USB_STR_3 USB_STRING_DESCRIPTOR M 0 C 0 U 0 0 H 0 I 0 D 0 0 G 0 E 0 N 0 E 0 R 0 I 0 C 0...

Page 312: ...the direction and type of packet sent in the report otherwise the contents of all reports are the same Report ID Packet Type Direction 1 Command OUT 2 Data OUT 3 Command IN 4 Data IN For all reports...

Page 313: ...ver 14 5 Get SetProperty Command Properties This section lists the properties of the GetProperty and SetProperty commands Table 14 57 Properties used by Get SetProperty Commands sorted by Value Proper...

Page 314: ...eter to GetProperty command identifies the segment See the device specific memory map for number of RAM segments the device contains SystemDeviceId No 10h 4 Value of the Kinetis System Device Identifi...

Page 315: ...USB CDC USB HID Reserved LPSPI Slave LPI2C Slave LPUART If the peripheral is available then the corresponding bit will be set in the property value All reserved bits must be set to 0 14 5 1 3 Availabl...

Page 316: ...iveSbFile command the host can send an SB file that contains various commands and data that will be executed on the Kinetis bootloader the target An unencrypted SB file can be flashed to the target on...

Page 317: ...an MMCAU set up structure The location in the configuration area relative to the BCA is at offset 0x20 as shown in the BCA layout in this document The pointer is a little endian memory location that...

Page 318: ...on integrity check Before application integrity testing the following fields in the bootloader configuration area must be set Set crcStartAddress to the start address that should be used for the CRC c...

Page 319: ...ail 1 Operation failed with a generic error kStatus_ReadOnly 2 Requested value cannot be changed because it is read only kStatus_OutOfRange 3 Requested value is out of range kStatus_InvalidArgument 4...

Page 320: ...m 10105 The checksum of a command tag block is invalid kStatusRomLdrCrc32Error 10106 The CRC 32 of the data for a load command is incorrect kStatusRomLdrUnknownCommand 10107 An unknown command was fou...

Page 321: ...tatus_AppCrcCheckInvalid 10403 CRC check is invalid because the BCA is invalid or the CRC parameters are unset all 0xFF bytes kStatus_AppCrcCheckOutOfRange 10404 CRC check is valid but addresses are o...

Page 322: ...Kinetis Bootloader Status Error Codes K32 L2A Reference Manual Rev 2 01 2020 322 NXP Semiconductors...

Page 323: ...a set of specialized operations to improve the throughput of software based security encryption decryption operations and message digest functions The CAU supports acceleration of the DES 3DES AES MD...

Page 324: ...ridge between the PPB interface and the CAU module Passes memory mapped commands and data on the PPB to from the CAU 4 entry FIFO Contains commands and input operands and the associated control captur...

Page 325: ...tate of the 4 entry command data FIFO Some basic integrity checks on PPB operations The set of implemented algorithms provides excellent support for network security standards such as SSL and IPsec Ad...

Page 326: ...256 algorithms Simple flexible programming model Ability to send up to three commands in one data write operation 15 5 Memory map Register definition The CAU contains multiple registers used by each...

Page 327: ...31 2 of the CASR must be written as 0 for compatibility with future versions of the CAU The codes listed in this section are used in the memory mapped commands For more details on this see CAU program...

Page 328: ...ster CAU0_CA8 32 R W 0000_0000h 15 5 3 329 15 5 1 Status Register CAUx_CASR CASR contains the status and configuration for the CAU Address F000_5000h base 0h offset F000_5000h Bit 31 30 29 28 27 26 25...

Page 329: ...criptions Field Description ACC Accumulator Stores results of various CAU commands 15 5 3 General Purpose Register CAUx_CAn The General Purpose Register is used in the CAU commands for storage of resu...

Page 330: ...equires a 15 bit command and optionally a 32 bit input operand for each CAU load PPB write The 15 bit command includes the 9 bit opcode and other bits statically formed by the CAU translator logic con...

Page 331: ...40 CAU Base Address 0x1B68 STR CAx LDR CAx RADR CAx ADR CAx ROTL CAx XOR CAx AESIC CAx AESC CAx Reserved terminated with illegal command Figure 15 3 CAU memory map 15 6 1 1 Direct loads The CAU suppor...

Page 332: ...ail of Indirect stores is shown in the figure below CAU base address 1 0 0 31 0 4 8 12 16 20 24 28 CAU_STR Rn Read address CAx 31 0 4 8 12 16 20 24 28 Read data Figure 15 6 Indirect store 15 6 2 CAU i...

Page 333: ...an error termination Within the second 2 KB region of the address space i e addr 11 1 only a 64 byte space is treated as a legal CAU store operation The allowable addresses are defined as addr 11 0 10...

Page 334: ...ister CASR CAA and CAn Table 15 2 CAU commands Type Command name Description CMD Operation 8 7 6 5 4 3 2 1 0 Direct load CNOP No Operation 0x000 Indirect load LDR Load Reg 0x01 CAx Op1 CAx Indirect st...

Page 335: ...ash Shift 0x130 CAA 5 CAA CAA CA0 CA0 CA1 CA1 30 CA2 CA2 CA3 CA3 CA4 Direct load MDS Message Digest Shift 0x140 CA3 CAA CAA CA1 CA1 CA2 CA2 CA3 Direct load SHS2 Secure Hash Shift 2 0x150 CAA CA0 CA0 C...

Page 336: ...Ax The table below shows an example Table 15 3 RADR command example Operand CAx before CAx after 0x0102_0304 0xA0B0_C0D0 0xA4B3_C2D1 15 6 3 6 Add Register to Accumulator ADRA The ADRA command adds CAx...

Page 337: ...3 13 AES Column Operation AESC The AESC command performs the AES column operation on the contents of CAx It then performs an exclusive or of that result with the source operand specified by the write...

Page 338: ...0102_0304 CA1 0x050A_0F04 0x0506_0708 CA2 0x090E_0308 0x090A_0B0C CA3 0x0D02_070C 0x0D0E_0F00 Where row 1 CA0 31 24 CA1 31 24 CA2 31 24 CA3 31 24 row 2 CA0 23 16 CA1 23 16 CA2 23 16 CA3 23 16 row 3 CA...

Page 339: ...a left shift by one also occurs and the values C1 and D1 store back to CA0 and CA1 respectively The DC bit should be cleared for encrypt operations If the CP bit is set and a key parity error is dete...

Page 340: ...20 Secure Hash Shift SHS The SHS command does a set of parallel register to register move and shift operations for implementing SHA 1 The following source and destination assignments are made Register...

Page 341: ...formation This section discusses how to initialize and use the CAU 15 7 1 Code example A code fragment is shown below as an example of how the CAU is used This example shows the round function of the...

Page 342: ...set CA2 0x4 set CA3 0x5 set CA4 0x6 set CA5 0x7 set CA6 0x8 set CA7 0x9 set CA8 0xA CAU Commands set CNOP 0x000 set LDR 0x010 set STR 0x020 set ADR 0x030 set RADR 0x040 set ADRA 0x050 set XOR 0x060 se...

Page 343: ...CA3 CA2 CA3 set HF2C 0x6 SHA 256 Ch CA4 CA5 CA4 CA6 set HF2M 0x7 SHA 256 Maj CA0 CA1 CA0 CA2 CA1 CA2 set HF2S 0x8 SHA 256 Sigma 0 ROTR2 CA0 ROTR13 CA0 ROTR22 CA0 set HF2T 0x9 SHA 256 Sigma 1 ROTR6 CA...

Page 344: ...Application initialization information K32 L2A Reference Manual Rev 2 01 2020 344 NXP Semiconductors...

Page 345: ...ss the full range of the supply voltage The 6 bit DAC is 64 tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed The 64 tap resi...

Page 346: ...internal functions Two software selectable performance levels Shorter propagation delay at the expense of higher power Low power with longer propagation delay DMA transfer support A comparison event...

Page 347: ...1 channel mux Operational over the entire supply range 16 1 4 CMP DAC and ANMUX diagram The following figure shows the block diagram for the High Speed Comparator DAC and ANMUX modules Chapter 16 Comp...

Page 348: ...e Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Reference Input 5 Reference Input 6 INP INM Sample input Figure 16 1 CMP DAC and ANMUX block diagram 16 1 5 CMP block...

Page 349: ...If CR1 WE 1 the comparator output will be sampled on every bus clock when WINDOW 1 to generate COUTA Sampling does NOT occur when WINDOW 0 The Filter block is bypassed when not in use The Filter bloc...

Page 350: ...4006_E005 MUX Control Register CMP0_MUXCR 8 R W 00h 16 2 6 355 400E_F000 CMP Control Register 0 CMP1_CR0 8 R W 00h 16 2 1 350 400E_F001 CMP Control Register 1 CMP1_CR1 8 R W 00h 16 2 2 351 400E_F002...

Page 351: ...reserved This read only field is reserved and always has the value 0 HYSTCTR Comparator hard block hysteresis control Defines the programmable hysteresis level The hysteresis values associated with ea...

Page 352: ...propagation delay and lower current consumption 1 High Speed HS Comparison mode selected In this mode CMP has faster output propagation delay and higher current consumption 3 INV Comparator INVERT All...

Page 353: ...on This field has no effect when CR1 SE 1 In that case the external SAMPLE signal is used to determine the sampling period 16 2 4 CMP Status and Control Register CMPx_SCR Address Base address 3h offse...

Page 354: ...ed 1 Rising edge on COUT has occurred 1 CFF Analog Comparator Flag Falling Detects a falling edge on COUT when set during normal operation CFF is cleared by writing 1 to it During Stop modes CFF is le...

Page 355: ...This bit is used to enable to MUX pass through mode Pass through mode is always available but for some devices this feature must be always disabled due to the lack of package pins 0 Pass Through Mode...

Page 356: ...o INP and INM CMPO is high when the non inverting input is greater than the inverting input and is low when the non inverting input is less than the inverting input This signal can be selectively inve...

Page 357: ...le Individual modes are discussed below Table 16 1 Comparator sample filter controls Mode CR1 EN CR1 WE CR1 SE CR0 FILTER_C NT FPR FILT_PER Operation 1 0 X X X X Disabled See the Disabled mode 1 2A 1...

Page 358: ...used to drive a fault input for example for a motor control module such as FTM it must be configured to operate in Continuous mode so that an external fault can immediately pass through the comparato...

Page 359: ...sample window input The analog comparator block is powered and active CMPO may be optionally inverted but is not subject to external sampling or filtering Both window control and filter blocks are com...

Page 360: ...ed and active The path from analog inputs to COUTA is combinational unclocked Windowing control is completely bypassed COUTA is sampled whenever a rising edge is detected on the filter block clock inp...

Page 361: ...al internally derived 16 3 1 4 Sampled Filtered mode s 4A 4B In Sampled Filtered mode the analog comparator block is powered and active The path from analog inputs to COUTA is combinational unclocked...

Page 362: ...WINDOW SAMPLE 1 0 EN PMODE HYSTCTR 1 0 divided bus clock CMPO 0x01 Internal bus Polarity select Window control Filter block Interrupt control Clock prescaler To other SOC functions Figure 16 6 Sample...

Page 363: ...4B is that now CR0 FILTER_CNT 1 which activates filter operation 16 3 1 5 Windowed mode s 5A 5B The following figure illustrates comparator operation in the Windowed mode ignoring latency of the analo...

Page 364: ...R bus clock COS 0x01 IER F CFR F WINDOW SAMPLE Polarity select Window control Filter block Interrupt control divided bus clock Clock prescaler CMPO Internal bus To other SOC functions Figure 16 9 Wind...

Page 365: ...pplication Depending upon the sampling rate and window placement COUT may not see zero crossing events detected by the analog comparator Sampling period and or window placement must be carefully consi...

Page 366: ...e last latched value is held when WINDOW 0 IRQ EN PMODE HYSCTR 1 0 INP INM FILTER_CNT INV COUT COUT OPE SE CMPO to PAD COUTA 0 1 WE 1 0 SE 0 CGMUX COS FILT_PER 0 1 FILT_PER bus clock COS IER F CFR F W...

Page 367: ...ted The CMP output pin is latched and does not reflect the compare output state The positive and negative input voltage can be supplied from external pins or the DAC output The MCU can be brought out...

Page 368: ...filtering and the amount of filtering is dependent on user requirements Filtering can become more useful in the absence of an external hysteresis circuit Without external hysteresis high frequency osc...

Page 369: ...ILTER_CNT The values of FPR FILT_PER or SAMPLE period and CR0 FILTER_CNT must also be traded off against the desire for minimal latency in recognizing actual comparator output transitions The probabil...

Page 370: ...serted When Then SCR IER and SCR CFR are set The interrupt request is asserted SCR IEF and SCR CFF are set The interrupt request is asserted SCR IER and SCR CFR are cleared for a rising edge interrupt...

Page 371: ...n for details 16 6 CMP Asynchronous DMA support The comparator can remain functional in STOP modes When DMA support is enabled by setting SCR DMAEN and the interrupt is enabled by setting SCR IER SCR...

Page 372: ...1 and Vin2 The module can be powered down or disabled when not in use When in Disabled mode DACO is connected to the analog ground VOSEL 5 0 DACO MUX MUX DACEN Vin VRSEL Vin1 Vin2 Figure 16 12 6 bit D...

Page 373: ...on the CMP must be enabled If the DAC is to be used as a reference to the CMP it must also be enabled CMP Trigger mode depends on an external timer resource to periodically enable the CMP and 6 bit DA...

Page 374: ...CMP Trigger Mode K32 L2A Reference Manual Rev 2 01 2020 374 NXP Semiconductors...

Page 375: ...the CRC module include Hardware CRC generator circuit using a 16 bit or 32 bit programmable shift register Programmable initial seed value and polynomial Option to transpose input data or output data...

Page 376: ...r Stop Any CRC calculation in progress stops when the MCU enters a low power mode that disables the module clock It resumes after the clock is enabled or via the system reset for exiting the low power...

Page 377: ...6 5 4 3 2 1 0 R HU HL LU LL W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_DATA field descriptions Field Description 31 24 HU CRC High Upper Byte In 16 bit CRC mode CTRL...

Page 378: ...Polynominal Half word Writable and readable in 32 bit CRC mode CTRL TCRC is 1 This field is not writable in 16 bit CRC mode CTRL TCRC is 0 LOW Low Polynominal Half word Writable and readable in both...

Page 379: ...byte are transposed 27 Reserved This field is reserved This read only field is reserved and always has the value 0 26 FXOR Complement Read Of CRC Data Register Some CRC protocols require the final che...

Page 380: ...bit CRC To compute a 16 bit CRC 1 Clear CRC_CTRL TCRC to enable 16 bit CRC mode 2 Program the transpose and complement options in the CTRL register as required for the CRC calculation See Transpose fe...

Page 381: ...re and CRC result complement for details 17 3 3 Transpose feature By default the transpose feature is not enabled However some CRC standards require the input data and or the final checksum to be tran...

Page 382: ...gure 17 2 Transpose type 01 3 CTRL TOT or CTRL TOTR is 10 Both bits in bytes and bytes are transposed reg 31 0 becomes reg 0 7 reg 8 15 reg 16 23 reg 24 31 31 31 0 0 Figure 17 3 Transpose type 10 4 CT...

Page 383: ...e after transposition resides in the CRC HU HL fields The user software must account for this situation when reading the 16 bit CRC result so reading 32 bits is preferred 17 3 4 CRC result complement...

Page 384: ...Functional description K32 L2A Reference Manual Rev 2 01 2020 384 NXP Semiconductors...

Page 385: ...alog comparator op amps or ADC 18 2 Features The features of the DAC module include On chip programmable reference generator output The voltage output range is from 1 4096 Vin to Vin and the step is 1...

Page 386: ...BTIEN DACBFRPBF DACBBIEN OR dac_interrupt DACTRGSE LPEN DACRFS DACREF_1 Vin Vo Data Buffer Figure 18 1 DAC block diagram 18 4 Memory map register definition The DAC has registers to control analog com...

Page 387: ...0_DAT8L 8 R W 00h 18 4 1 388 4006_A011 DAC Data High Register DAC0_DAT8H 8 R W 00h 18 4 2 388 4006_A012 DAC Data Low Register DAC0_DAT9L 8 R W 00h 18 4 1 388 4006_A013 DAC Data High Register DAC0_DAT9...

Page 388: ...ACx_DATnH field descriptions Field Description 7 4 Reserved This field is reserved This read only field is reserved and always has the value 0 DATA1 DATA1 When the DAC Buffer is not enabled DATA 11 0...

Page 389: ...uffer read pointer is not zero 1 The DAC buffer read pointer is zero 0 DACBFRPBF DAC Buffer Read Pointer Bottom Position Flag 0 The DAC buffer read pointer is not equal to C2 DACBFUP 1 The DAC buffer...

Page 390: ...oft trigger is valid 3 LPEN DAC Low Power Control NOTE See the 12 bit DAC electrical characteristics of the device data sheet for details on the impact of the modes below 0 High Power mode 1 Low Power...

Page 391: ...er Watermark Select Controls when SR DACBFWMF is set When the DAC buffer read pointer reaches the word defined by this field which is 1 4 words away from the upper limit DACBUP SR DACBFWMF will be set...

Page 392: ...DACDAT0 11 0 or the data from the DAC data buffer to a stepped analog output voltage The output voltage range is from Vin to Vin 4096 and the step is Vin 4096 18 5 1 DAC data buffer operation When the...

Page 393: ...increases by one every time the trigger occurs When the read pointer reaches the upper limit it goes to 0 directly in the next trigger event Buffer Swing mode This mode is similar to the normal mode H...

Page 394: ...ait mode The DAC will operate normally if enabled Stop mode If enabled the DAC module continues to operate normally with the hardware trigger initiating the conversion In low power stop modes the DAC...

Page 395: ...details of this module s instances see the chip configuration information 19 1 1 Overview The Direct Memory Access Multiplexer DMAMUX routes DMA sources called slots to any of the 8 DMA channels This...

Page 396: ...up to four always on slots can be routed to 8 channels 8 independently selectable DMA channel routers The first four channels additionally provide a trigger functionality Each channel router can be a...

Page 397: ...for channels 0 3 19 2 External signal description The DMAMUX has no external pins 19 3 Memory map register definition This section provides a detailed description of all memory mapped registers in th...

Page 398: ...onfiguration of the DMAMux The DMA has separate channel enables disables which should be used to disable or reconfigure a DMA channel 1 DMA channel is enabled 6 TRIG DMA Channel Trigger Enable Enables...

Page 399: ...4 channels of the DMAMUX provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes frames or packets at fixed intervals without the need fo...

Page 400: ...vent has been seen This is illustrated in the following figure DMA request Peripheral request Trigger Figure 19 3 DMAMUX channel triggering normal operation After the DMA request has been serviced the...

Page 401: ...g a method to periodically read data from external devices and transfer the results into memory without processor intervention Using the GPIO ports to drive or sample waveforms By configuring the DMA...

Page 402: ...ses where software should initiate the start of a DMA transfer an always enabled DMA source can be used to provide maximum flexibility When activating a DMA channel via software subsequent executions...

Page 403: ...y enabled before use 19 5 2 Enabling and configuring sources To enable a source with periodic triggering 1 Determine with which DMA channel the source will be associated Note that only the first 4 DMA...

Page 404: ...ng the channel 3 Write 0x85 to CHCFG1 The following code example illustrates steps 1 and 3 above In File registers h define DMAMUX_BASE_ADDR 0x40021000 Example only Following example assumes char is 8...

Page 405: ...ates steps 2 and 3 above In File registers h define DMAMUX_BASE_ADDR 0x40021000 Example only Following example assumes char is 8 bits volatile unsigned char CHCFG0 volatile unsigned char DMAMUX_BASE_A...

Page 406: ...In File main c include registers h CHCFG8 0x00 CHCFG8 0x87 Initialization application information K32 L2A Reference Manual Rev 2 01 2020 406 NXP Semiconductors...

Page 407: ...complex data transfers with minimal intervention from a host processor The hardware microarchitecture includes A DMA engine that performs Source address and destination address calculations Data move...

Page 408: ...All the channels provide the same functionality This structure allows data transfers associated with one channel to be preempted after the completion of a read write sequence if a higher priority cha...

Page 409: ...es are equal the eDMA engine performs a series of source read destination write operations until the number of bytes specified in the minor loop byte count has moved For descriptors where the sizes ar...

Page 410: ...robin channel arbitration Channel completion reported via programmable interrupt requests One interrupt per channel which can be asserted at completion of major iteration count Programmable error ter...

Page 411: ...de the DMA attempts to complete its current transfer After the transfer completes the device enters Wait mode 20 3 Memory map register definition The eDMA s programming model is partitioned into two r...

Page 412: ...rns the value of zero Writes to reserved bits in a register are ignored Reading or writing a reserved memory location generates a bus error DMA memory map Absolute address hex Register name Width in b...

Page 413: ...Register DMA0_DCHPRI1 8 R W See section 20 3 21 440 4000_8103 Channel n Priority Register DMA0_DCHPRI0 8 R W See section 20 3 21 440 4000_8104 Channel n Priority Register DMA0_DCHPRI7 8 R W See sectio...

Page 414: ..._TCD1_NBYTES_MLNO 32 R W Undefined 20 3 25 443 4000_9028 TCD Signed Minor Loop Offset Minor Loop Mapping Enabled and Offset Disabled DMA0_TCD1_NBYTES_MLOFFNO 32 R W Undefined 20 3 26 443 4000_9028 TCD...

Page 415: ...A0_TCD2_CSR 16 R W Undefined 20 3 34 450 4000_905E TCD Beginning Minor Loop Link Major Loop Count Channel Linking Enabled DMA0_TCD2_BITER_ELINKYES 16 R W Undefined 20 3 35 453 4000_905E TCD Beginning...

Page 416: ...32 R W Undefined 20 3 27 445 4000_908C TCD Last Source Address Adjustment DMA0_TCD4_SLAST 32 R W Undefined 20 3 28 446 4000_9090 TCD Destination Address DMA0_TCD4_DADDR 32 R W Undefined 20 3 29 446 40...

Page 417: ...BITER_ELINKNO 16 R W Undefined 20 3 36 454 4000_90C0 TCD Source Address DMA0_TCD6_SADDR 32 R W Undefined 20 3 22 441 4000_90C4 TCD Signed Source Address Offset DMA0_TCD6_SOFF 16 R W Undefined 20 3 23...

Page 418: ...46 4000_90F4 TCD Signed Destination Address Offset DMA0_TCD7_DOFF 16 R W Undefined 20 3 30 447 4000_90F6 TCD Current Minor Loop Link Major Loop Count Channel Linking Enabled DMA0_TCD7_CITER_ELINKYES 1...

Page 419: ...y multiple fields a source enable bit SMLOE to specify the minor loop offset should be applied to the source address TCDn_SADDR upon minor loop completion a destination enable bit DMLOE to specify the...

Page 420: ...data transfer in the same fashion as the CX bit Stop the executing channel and force the minor loop to finish The cancel takes effect after the last write of the current read write sequence The ECX bi...

Page 421: ...tion 1 Any error causes the HALT bit to set Subsequently all service requests are ignored until the HALT bit is cleared 3 Reserved This field is reserved Reserved 2 ERCA Enable Round Robin Channel Arb...

Page 422: ...alue 0 14 CPE Channel Priority Error 0 No channel priority error 1 The last recorded error was a configuration error in the channel priorities Channel priorities are not unique 13 11 Reserved This fie...

Page 423: ...of a scatter gather operation after major loop completion if TCDn_CSR ESG is enabled TCDn_DLASTSGA is not on a 32 byte boundary 1 SBE Source Bus Error 0 No source bus error 1 The last recorded error...

Page 424: ...e DMA Request 5 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 4 ERQ4 Enable DMA Request 4 0 The DMA request signa...

Page 425: ...reserved and always has the value 0 7 EEI7 Enable Error Interrupt 7 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for correspon...

Page 426: ...anism to clear a given bit in the EEI to disable the error interrupt for a given channel The data value on a register write causes the corresponding bit in the EEI to be cleared Setting the CAEE bit p...

Page 427: ...the command is ignored This allows you to write multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 19h offset 4000_8019h Bit 7 6 5 4 3 2 1 0 Read...

Page 428: ...rd Reads of this register return all zeroes NOTE Disable a channel s hardware service request at the source before clearing the channel s ERQ bit Address 4000_8000h base 1Ah offset 4000_801Ah Bit 7 6...

Page 429: ...te registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Bh offset 4000_801Bh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAER 0 SERQ Reset 0 0 0 0 0 0 0 0 DMAx_SER...

Page 430: ...gisters as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Ch offset 4000_801Ch Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CADN 0 CDNE Reset 0 0 0 0 0 0 0 0 DMAx_CDNE fie...

Page 431: ...d Reads of this register return all zeroes Address 4000_8000h base 1Dh offset 4000_801Dh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAST 0 SSRT Reset 0 0 0 0 0 0 0 0 DMAx_SSRT field descriptions Field D...

Page 432: ...ou to write multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Eh offset 4000_801Eh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAEI 0 CERR Reset 0...

Page 433: ...you to write multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Fh offset 4000_801Fh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAIR 0 CINT Reset...

Page 434: ...fect on the corresponding channel s current interrupt status The CINT register is provided so the interrupt request for a single channel can easily be cleared without the need to perform a read modify...

Page 435: ...condition by setting the appropriate bit in this register The outputs of this register are enabled by the contents of the EEI and then routed to the interrupt controller During the execution of the i...

Page 436: ...s not occurred 1 An error in this channel has occurred 5 ERR5 Error In Channel 5 0 An error in this channel has not occurred 1 An error in this channel has occurred 4 ERR4 Error In Channel 4 0 An erro...

Page 437: ...ld Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 HRS7 Hardware Request Status Channel 7 The HRS bit for its respective channel remains...

Page 438: ...resent 1 A hardware service request for channel 3 is present 2 HRS2 Hardware Request Status Channel 2 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is...

Page 439: ...e for channel 6 0 Disable asynchronous DMA request for channel 6 1 Enable asynchronous DMA request for channel 6 5 EDREQ_5 Enable asynchronous DMA request in stop mode for channel 5 0 Disable asynchro...

Page 440: ...es with unique values otherwise a configuration error is reported The range of the priority value is limited to the values of 0 through 7 Address 4000_8000h base 100h offset 1d i where i 0d to 7d Bit...

Page 441: ...x x x x x x x x x x x x Notes x Undefined at reset DMAx_TCDn_SADDR field descriptions Field Description SADDR Source Address Memory address pointing to the source data 20 3 23 TCD Signed Source Addre...

Page 442: ...address and the SMOD field should be set to the appropriate value for the queue freezing the desired number of upper address bits The value programmed into this field specifies the number of lower ad...

Page 443: ...ed in each service request of the channel As a channel activates the appropriate TCD contents load into the eDMA engine and the appropriate reads and writes perform until the minor byte transfer count...

Page 444: ...The minor loop offset is applied to the SADDR 30 DMLOE Destination Minor Loop Offset enable Selects whether the minor loop offset is applied to the destination address upon minor loop completion 0 Th...

Page 445: ...ion Address 4000_8000h base 1008h offset 32d i where i 0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SMLOE DMLOE MLOFF W Reset x x x x x x x x x x x x x x x x Bit 15 14 13 12 11 10 9...

Page 446: ...tion count is completed additional processing is performed 20 3 28 TCD Last Source Address Adjustment DMAx_TCDn_SLAST Address 4000_8000h base 100Ch offset 32d i where i 0d to 7d Bit 31 30 29 28 27 26...

Page 447: ...ned Offset Sign extended offset applied to the current destination address to form the next state value as each destination write is completed 20 3 31 TCD Current Minor Loop Link Major Loop Count Chan...

Page 448: ...inking is enabled ELINK 1 then after the minor loop is exhausted the eDMA engine initiates a channel service request to the channel defined by this field by setting that channel s TCDn_CSR START bit C...

Page 449: ...suppressed in favor of the MAJORELINK channel linking NOTE This bit must be equal to the BITER ELINK bit otherwise a configuration error is reported 0 The channel to channel linking is disabled 1 The...

Page 450: ...stination address to the initial value or adjust the address to reference the next data structure This field uses two s complement notation for the final destination address adjustment Otherwise This...

Page 451: ...e cleared to write the MAJORELINK or ESG bits 6 ACTIVE Channel Active This flag signals the channel is currently in execution It is set when channel service begins and is cleared by the eDMA as the mi...

Page 452: ...eDMA engine is CITER BITER 1 This halfway point interrupt request is provided to support double buffered also known as ping pong schemes or other types of data movement where the processor needs an e...

Page 453: ...be set equal to the corresponding CITER field otherwise a configuration error is reported As the major iteration count is exhausted the contents of this field are reloaded into the CITER field 0 The...

Page 454: ...s the minor loop this flag enables the linking to another channel defined by BITER LINKCH The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR S...

Page 455: ...eld If the channel is configured to execute a single service request the initial values of BITER and CITER should be 0x0001 20 4 Functional description The operation of the eDMA is described in the fo...

Page 456: ...hrough the control module then into the program model and channel arbitration In the next cycle the channel arbitration performs using the fixed priority or round robin algorithm After arbitration is...

Page 457: ...rocessing continues until the minor byte count has transferred After the minor byte count has moved the final phase of the basic data flow is performed In this segment the address path logic performs...

Page 458: ...legal setting in the transfer control descriptor or an illegal priority register setting in Fixed Arbitration mode or An error termination to a bus master read or write cycle A configuration error is...

Page 459: ...orted if the scatter gather address DLAST_SGA is not aligned on a 32 byte boundary If minor loop channel linking is enabled upon channel completion a configuration error is reported when the link is a...

Page 460: ...e data transfer in the event the full data transfer is no longer needed The cancel transfer bit does not abort the channel It simply stops the transferring of data and then retires the channel through...

Page 461: ...ng This allows for a pool of low priority large data moving channels to be defined These low priority channels can be configured to not preempt each other thus preventing a low priority channel from c...

Page 462: ...0 38 4 66 7 MHz 32 bit 133 3 66 7 53 3 83 3 MHz 32 bit 166 7 83 3 66 7 100 0 MHz 32 bit 200 0 100 0 80 0 133 3 MHz 32 bit 266 7 133 3 106 7 150 0 MHz 32 bit 300 0 150 0 120 0 Internal SRAM to internal...

Page 463: ...from the local memory Depending on the state of the crossbar switch arbitration at the system bus may insert an additional cycle of delay here 8 11 8 12 The last part of the TCD is read in This cycle...

Page 464: ...ula operands Operand Description PEAKreq Peak request rate freq System frequency entry Channel startup 4 cycles read_ws Wait states seen during the system bus read data phase write_ws Wait states seen...

Page 465: ...of the eDMA peripheral request signals For the peak request rate calculations above the arbitration and request registering is absorbed in or overlaps the previous executing channel Note When channel...

Page 466: ...abled If the major loop is exhausted further post processing executes such as interrupts major loop channel linking and scatter gather operations if enabled Table 20 8 TCD Control and Status fields TC...

Page 467: ...of bytes added to current address after each transfer often the same value as xSIZE Each DMA source S and destination D has its own Address xADDR Size xSIZE Offset xOFF Modulo xMOD Last Address Adjus...

Page 468: ...tion considerations for the eDMA 20 5 3 1 Fixed channel arbitration In this mode the channel service request from the highest priority channel is selected to execute 20 5 3 2 Round robin channel arbit...

Page 469: ...ite to the TCDn_CSR START bit requests channel service 2 The channel is selected by arbitration for servicing 3 eDMA engine writes TCDn_CSR DONE 0 TCDn_CSR START 0 TCDn_CSR ACTIVE 1 4 eDMA engine read...

Page 470: ...2 TCDn_SLAST 32 TCDn_DLAST_SGA 32 This would generate the following sequence of events 1 First hardware that is eDMA peripheral request for channel service 2 The channel is selected by arbitration for...

Page 471: ...ation transfers are executed as follows a Read byte from location 0x1010 read byte from location 0x1011 read byte from 0x1012 read byte from 0x1013 b Write 32 bits to location 0x2010 first iteration o...

Page 472: ...d Here a circular buffer is created where the address wraps to the original value while the 28 upper address bits 0x1234567x retain their original value In this example the source address is set to 0x...

Page 473: ...grammer s model The TCD status bits execute the following sequence for a hardware activated channel Stage TCDn_CSR bits State START ACTIVE DONE 1 0 0 0 Channel service request via hardware peripheral...

Page 474: ...are set simultaneously in the global TCD map a higher priority channel is actively preempting a lower priority channel 20 5 6 Channel Linking Channel linking or chaining is a mechanism where one chann...

Page 475: ...lowing table summarizes how a DMA channel can link to another DMA channel i e use another channel s TCD at the end of a loop Table 20 10 Channel Linking Parameters Desired Link Behavior TCD Control Fi...

Page 476: ...el The TCD major e_link would be set in the programmer s model but it would be unclear whether the actual link was made before the channel retired The following coherency model is recommended when exe...

Page 477: ...reading the major linkch field and the e_sg bit with a single read For both dynamic channel linking and scatter gather requests the TCD local memory controller forces the TCD major e_link and TCD e_sg...

Page 478: ...using major loop channel linking For a channel using major loop channel linking the coherency model described here may be used for a dynamic scatter gather request This method uses the TCD dlast_sga...

Page 479: ...channel To suspend an active DMA channel 1 Stop the DMA service request at the peripheral first Confirm it has been disabled by reading back the appropriate register in the peripheral 2 Check Hardwar...

Page 480: ...te channel If no service request is present disable the DMA channel by clearing the channel s ERQ bit If a service request is present wait until the request has been processed and the HRS bit reads ze...

Page 481: ...transmitter and receiver Automatic NACK generation on parity error and receiver FIFO overflow error Support for both Inverse and Direct conventions Re transmission of byte upon Smart Card NACK reques...

Page 482: ...of port logic on Smart Card presence detect Support for 8 bit LRC and 16 bit CRC generation for bytes sent out from transmitter and checking incoming message checksum for receiver 21 2 Block Diagram F...

Page 483: ...al ETU clocks for transmitter and receiver The transmitter comprises of a 4 byte deep FIFO to store the bytes to be sent to the Smart Card These bytes are sent to the Smart Card serially by the transm...

Page 484: ...ertion of the clock reset and VCC signals to Smart Card It can do so manually software needs to explicitly write the necessary bits or using auto power down wherein the module can itself power down th...

Page 485: ...gister EMVSIM0_RX_THD 32 R W 0000_0001h 21 5 7 496 4004_E01C Transmitter Threshold Register EMVSIM0_TX_THD 32 R W 0000_000Fh 21 5 8 496 4004_E020 Receive Status Register EMVSIM0_RX_STATUS 32 w1c 0000_...

Page 486: ...egister provides details on the parameter settings that were used while including this module in the chip Address 4004_E000h base 4h offset 4004_E004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 487: ...Counter is active while RCV_EN or XMT_EN are set 00 Disabled Reset default 01 Card Clock 10 Receive Clock 11 ETU Clock transmit clock 9 8 GPCNT1_CLK_ SEL General Purpose Counter 1 Clock Select Select...

Page 488: ...reserved This read only field is reserved and always has the value 0 DIVISOR_ VALUE Divisor F D Value The value written to this register will be used to generate the ETU bit period that will be used...

Page 489: ...BWT_EN Block Wait Time Counter Enable Writing a 1 to this bit will enable the BWT and BGT functions The BWT and BGT functions can then be individually selected using the interrupt mask 0 Disable BWT...

Page 490: ...al this bit can be set accordingly 0 Bits in the input byte will not be reversed i e 7 0 will remain 7 0 before the CRC calculation default 1 Bits in the input byte will be reversed i e 7 0 will becom...

Page 491: ...16 RCV_EN Receiver Enable Used to enable disable the EMV SIM receiver block Once the transmitter has completed its operation the software must enable the receiver using this bit It can be set to 0 du...

Page 492: ...operation default 1 EMV SIM Transmitter held in Reset 8 FLSH_RX Flush Receiver Bit This bit operates as an EMV SIM receiver reset The transmit portion of the EMV SIM module is not affected This bits c...

Page 493: ..._IM GPCNT1_IM BGT_ ERR_ IM BWT_ERR_IM RNACK_IM CWT_ERR_IM GPCNT0_IM TDT_IM TFF_IM TNACK_IM TFE_IM ETC_IM RFO_IM TC_IM RDT_IM W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EMVSIMx_INT_MASK field descriptions...

Page 494: ...he RX_STATUS register to generate EMV SIM interrupts 0 RTE interrupt enabled 1 RTE interrupt masked default 9 CWT_ERR_IM Character Wait Time Error Interrupt Mask Used to enable disable the ability of...

Page 495: ...the TX_STATUS register to generate EMV SIM interrupts 0 ETC interrupt enabled 1 ETC interrupt masked default 2 RFO_IM Receive FIFO Overflow Interrupt Mask Used to enable disable the ability of the RFO...

Page 496: ...ot be set 0 RTE will set after programmed value of NACKs are received 7 4 Reserved This field is reserved RDT Receiver Data Threshold Value Determines the number of bytes that must exist in the Receiv...

Page 497: ...r 2 nacks are received at most 1 retransmission occurs 3 TNTE will be set after 3 nacks are received at most 2 retransmissions occurs N TNTE will be set after N nacks are received at most N 1 retransm...

Page 498: ...31 25 Reserved This field is reserved This read only field is reserved and always has the value 0 24 22 RX_CNT Receive FIFO Byte Count These bits indicate the number of bytes stored in the receive FIF...

Page 499: ...et by the block wait time registers 0 Block wait time not exceeded 1 Block wait time was exceeded 9 RTE Received NACK Threshold Error Flag Used to indicate whether the number of consecutive NACK s gen...

Page 500: ...es left in the FIFO below the RDT 3 0 level Another way to clear the flag is to set the RDT 3 0 level higher than the number of unread bytes currently in the FIFO The RDTF flag will create an interrup...

Page 501: ...0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 GPCNT1_TO GPCNT0_TO TDTF TFF TCF ETCF TFE 0 TNTE W w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 EMVSIMx_TX_STATUS field descr...

Page 502: ...be cleared by writing enough bytes into the transmit FIFO so as to take the number of bytes in the FIFO above the TDT 3 0 level Another way to clear the flag is to set the TDT 3 0 level lower than the...

Page 503: ...successfully TFE will also be set when the TNTE flag is set The TFE flag will create an interrupt if TFE_IM in the INT_MASK register is low The TFE bit is a write one to clear bit 0 Transmit FIFO is n...

Page 504: ...ld is reserved and always has the value 0 27 SPDES SIM Presence Detect Edge Select Controls which edge of the Smart Card Presence Detect pin is used to detect the presence of the Smart Card 0 Falling...

Page 505: ...No effect default 1 Start Auto Powerdown or Power Down is in progress 6 Reserved This field is reserved This read only field is reserved and always has the value 0 5 SCSP Smart Card Clock Stop Polari...

Page 506: ...y Setting the SPD bit in this register by software Assertion of the RTE bit in the RX_STATUS register Assertion of the SPDIF bit when the interrupt is used for detecting card removal Manual Power Down...

Page 507: ...r EMVSIMx_TX_GETU Address 4004_E000h base 34h offset 4004_E034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 GETU W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 508: ...CWT Character Wait Time Value The value written to this register will specify the number of ETU times allowed between characters Default is 0xFFFF 21 5 16 Block Wait Time Value Register EMVSIMx_BWT_V...

Page 509: ..._GPCNT0_VAL Address 4004_E000h base 44h offset 4004_E044h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 GPCNT0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1...

Page 510: ...ransmit clock Example ATR arrival time and ATR duration Functional Description 21 6 1 Initialization 21 6 1 1 Configuring EMV SIM The first operation that must be done is to configure the EMV SIM inte...

Page 511: ...le if XMT_EN 1 and RCV_EN 0 and in order to enable the receiver first write to CTRL register should make XMT_EN 0 and second write to CTRL register should make RCV_EN 1 21 6 1 2 Configuring Receiver T...

Page 512: ...n the characters transmitted by writing to the GETU 7 0 bits in TX_GETU register Configure the desired data threshold in TX_THD register Enable necessary interrupts by clearing respective bits in the...

Page 513: ...ard is to provide power and a clock signal to the card Once the card is detected as present using the presence detect features or some other method the Smart Card should be powered up according to the...

Page 514: ...determine if the card has been inserted or removed The occurrence of the edge specified by SPDES bit will cause the following SPDIF to be set if the SPDIM mask is clear an interrupt to the CPU and if...

Page 515: ...cter and determine the data format when it is placed in the initial character mode by setting the ICM bit in CTRL register When placed in this mode the EMV SIM module samples in the input line and wai...

Page 516: ...one of the general purpose counter as a timeout during initial character mode When the receiver is in initial character mode all received bytes will continue to be placed into the receive FIFO whether...

Page 517: ...use the transmitter to transmit a NACK if ANACK 1 in CTRL register without software needed to enable transmitter for this and request re transmission of the current byte Framing Error Detection The re...

Page 518: ...t bits of two consecutive characters received from the Smart Card The value of CWT can range from 12 ETU to 32779 ETU The EMV SIM module provides a 16 bit counter with programmable comparator clocked...

Page 519: ...re set All bytes remaining in the transmit FIFO are lost There is no way to restart the transmission on the next byte in the FIFO The transmitter remains frozen until TNTE is cleared by software The o...

Page 520: ...T 1 Smart Cards The EMV SIM module provides hardware support for T 1 type Smart Cards These type of cards present several requirements above and beyond the standard T 0 cards The features provided to...

Page 521: ...as the minimum delay between the start bits of the last character of a transmitted block and the first character of the next received block The value of BGT is 22 ETU The EMV SIM module supports the B...

Page 522: ...C This block can be enabled through the CRC_EN bit in the CTRL register This block performs a polynomial based check on all received or transmitted characters The polynomial used for calculating the C...

Page 523: ...r the last character in the Transmit FIFO is sent 21 6 6 Message Handling The EMV SIM module has FIFOs on both transmit and receive side for handling all message bytes 21 6 6 1 Transmit FIFO A 4 byte...

Page 524: ...he RDTF bit is asserted in the RX_STATUS register An interrupt will be asserted if the RDT_IM bit in the INT_MASK is cleared If DMA access to RX_FIFO is enabled the DMA request to read the Rx FIFO wil...

Page 525: ...bits of previous character and the START bit of next character For a Guard Time programmed as 0xFF in GETU 7 0 bits of TX_GETU register the transmitter inserts one STOP bit instead of two 21 6 7 2 Ch...

Page 526: ...R flag will be set and an interrupt generated If the time is less than the value in the BGT_VAL register then the BGT_ERR flag will be set and an interrupt generated The block wait timer can be config...

Page 527: ...1 to the BWT_ERR or CWT_ERR bit in the RX_STATUS register 21 6 7 5 General Purpose Timers The EMV SIM module provides TWO 16 bit counters for use when timing events during Smart Card communication Th...

Page 528: ...o configure both general purpose timers Program counter comparator using the GPCNT0 1_VAL register Enable the conditions described above using the CTRL register Select desired clock source for the Gen...

Page 529: ...Smart Cards meet certain timing restrictions One of these is the time from the de assertion of the card reset to the beginning of the ATR sequence The EMV SIM module s General Purpose Counter can be...

Page 530: ...in the CTRL register Adjust the stop clock polarity by modifying the value of the SCSP bit in the PCSR register Adjust the level of transmit NACK re transmissions allowed by modifying the value of the...

Page 531: ...tter for 11 ETU transmissions Disable NACK capability by clearing the ONACK and ANACK bits in the CTRL register T 1 cards do not allow NACKs Adjust the stop clock polarity by modifying the value of th...

Page 532: ...bit during the PPS exchange Enable the transmitter by setting the XMT_EN bit in the CTRL register Write the characters to be sent as response max 4 to the transmit FIFO using the TX_BUF register At t...

Page 533: ...plementation of digital logic functions on chip and configurable interaction of internal and external modules Programmable state machine for offloading basic system control functions from CPU 22 1 2 F...

Page 534: ...conditions Programmable logic mode for integrating external digital logic functions on chip or combining pin shifter timer functions to generate complex outputs Programmable state machine for offloadi...

Page 535: ...to complete any pending operation before acknowledging low leakage mode entry Debug Can continue operating provided the Debug Enable bit CTRL DBGE is set 22 1 5 FlexIO Signal Descriptions Signal Descr...

Page 536: ...0000000h 400CA200h 400CA21Ch Shifter Buffer N SHIFTBUF0 SHIFTBUF7 32 RW 00000000h 400CA280h 400CA29Ch Shifter Buffer N Bit Swapped SHIFTBUFBIS0 SHIFTBUFBIS7 32 RW 00000000h 400CA300h 400CA31Ch Shifter...

Page 537: ...ajor Version Number This read only field returns the major version number for the module specification 23 16 MINOR Minor Version Number This read only field returns the minor version number for the mo...

Page 538: ...1 0 R TIMER SHIFTER W Reset 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 22 2 1 3 4 Fields Field Function 31 24 TRIGGER Trigger Number Number of external triggers implemented 23 16 PIN Pin Number Number of Pins im...

Page 539: ...disabled in low leakage stop modes 0b FlexIO enabled in Doze modes 1b FlexIO disabled in Doze modes 30 DBGE Debug Enable Enables FlexIO operation in Debug mode 0b FlexIO is disabled in debug modes 1b...

Page 540: ...ers except the Control Register are reset 0 FLEXEN FlexIO Enable 0b FlexIO module is disabled 1b FlexIO module is enabled 22 2 1 5 Pin State PIN 22 2 1 5 1 Address Register Offset PIN 400CA00Ch 22 2 1...

Page 541: ...ared when SHIFTBUF register is read For SMOD Transmit the status flag is set when SHIFTBUF data has been transferred to the Shifter SHIFTBUF is empty or when initially configured for SMOD Transmit and...

Page 542: ...ERR 400CA014h 22 2 1 7 2 Function 22 2 1 7 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SEF...

Page 543: ...a match has occured between SHIFTBUF and Shifter For SMOD Logic the error flag is set when the output of the programmable logic block has asserted Can be cleared by writing logic one to the flag For...

Page 544: ...e value in the compare register In 16 bit counter mode the timer status flag is set when the 16 bit counter equals zero and decrements this also causes the counter to reload with the value in the comp...

Page 545: ...Enable SHIFTEIEN 22 2 1 10 1 Address Register Offset SHIFTEIEN 400CA024h 22 2 1 10 2 Function 22 2 1 10 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0...

Page 546: ...Offset TIMIEN 400CA028h 22 2 1 11 2 Function 22 2 1 11 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 547: ...2 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SSDE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 2 1 12 4 Fields Field Function 31 8 7 0 S...

Page 548: ...6 5 4 3 2 1 0 R 0 STATE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 2 1 13 4 Fields Field Function 31 3 2 0 STATE Current State Pointer The current state field maintains a pointer to keep track of the...

Page 549: ...0 SMOD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 2 1 14 3 Fields Field Function 31 27 26 24 TIMSEL Timer Select Selects which Timer is used for controlling the logic shift register and generating th...

Page 550: ...of the Timer 011b Reserved 100b Match Store mode Shifter data is compared to SHIFTBUF content on expiration of the Timer 101b Match Continuous mode Shifter data is continuously compared to SHIFTBUF co...

Page 551: ...for PWIDTH 4 7 16 bit shift for PWIDTH 8 15 32 bit shift for PWIDTH 16 31 For Shifters which support parallel transmit SHIFTER0 SHIFTER4 or parallel receive SHIFTER3 SHIFTER7 this register field toget...

Page 552: ...a start bit For SMOD Receive or Match Store this field allows automatic start bit checking if the selected timer has also enabled a start bit For SMOD State this field is used to disable state output...

Page 553: ...checked either continuosly Match Continous mode or when the Timer expires Match Store mode SHIFTBUF 15 0 can be used to mask the match result 1 mask 0 no mask In Match Store mode Shifter data 31 16 i...

Page 554: ...7 16 R SHIFTBUFBIS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SHIFTBUFBIS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 2 1 17 4 Fields Field Function 31 0 SHIFT...

Page 555: ...SHIFTBUFBYS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SHIFTBUFBYS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 2 1 18 4 Fields Field Function 31 0 SHIFTBUFBYS...

Page 556: ...17 16 R SHIFTBUFBBS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SHIFTBUFBBS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 2 1 19 4 Fields Field Function 31 0 SHIF...

Page 557: ...Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 2 1 20 4 Fields Field Function 31 30 29 24 TRGSEL Trigger Select The valid values for TRGSEL will depend on the FLEXIO_PARAM register When TRGSRC 1 the valid v...

Page 558: ...IMOD Timer Mode In 8 bit counter mode the lower 8 bits of the counter and compare register are used to configure the baud rate of the timer shift clock and the upper 8 bits are used to configure the s...

Page 559: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 TIMDIS 0 TIMENA 0 TSTOP 0 TSTA RT 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 2 1 21 4 Fields Field Function 31 26 25 24 TIMOUT Timer Output Configures the initi...

Page 560: ...10b Timer reset on Trigger rising edge 111b Timer reset on Trigger rising or falling edge 15 14 12 TIMDIS Timer Disable Configures the condition that causes the Timer to be disabled and stop decrement...

Page 561: ...is enabled on timer disable 11b Stop bit is enabled on timer compare and timer disable 3 2 1 TSTART Timer Start Bit When start bit is enabled configured shifters will output the contents of the start...

Page 562: ...8 bit counters PWM mode the lower 8 bits configure the high period of the output to CMP 7 0 1 and the upper 8 bits configure the low period of the output to CMP 15 8 1 In 16 bit counter mode the comp...

Page 563: ...s to this register are nibble swapped within each byte Reads return SHIFTBUF 27 24 SHIFTBUF 31 28 SHIFTBUF 19 16 SHIFTBUF 23 20 SHIFTBUF 11 8 SHIFTBUF 15 12 SHIFTBUF 3 0 SHIFTBUF 7 4 22 2 1 24 Shifter...

Page 564: ...ft Buffer Alias to SHIFTBUF register except reads writes to this register are half word swapped Reads return SHIFTBUF 15 0 SHIFTBUF 31 24 22 2 1 25 Shifter Buffer N Nibble Swapped SHIFTBUFNISa 22 2 1...

Page 565: ...IFTBUF 7 4 SHIFTBUF 11 8 SHIFTBUF 15 12 SHIFTBUF 19 16 SHIFTBUF 23 20 SHIFTBUF 27 24 SHIFTBUF 31 28 22 3 Functional description 22 3 1 Shifter operation Shifters are responsible for buffering and shif...

Page 566: ...if a stop bit is enabled The Shifter Status Flag SHIFTSTAT SSF and any enabled interrupts or DMA requests will set when data has been loaded from the SHIFTBUF register into the Shifter or when the Shi...

Page 567: ...to mask the match result The Shifter Status Flag SHIFTSTAT SSF and any enabled interrupts or DMA requests will set when a match occurs and matched data has been stored into the SHIFTBUF register from...

Page 568: ...XIO_D7 0 timer_shift_neg TIMSEL TIMPOL PINCFG PINWIDTH SSTART SSTOP nstate 2 0 nstate_trigger SHIFTSTATE STATE i nstate attributes from other Shifters Figure 22 3 State Microarchitecture When Shifter...

Page 569: ...at reset however it can be written by the user to select a different Shifter for the initial state If the current state pointer selects a Shifter which is not configured for State mode then outputs wi...

Page 570: ...Logic Look up table for Shifter i SHIFTERi 0 FXIO_D x 3 1 FXIO_D x 2 FXIO_D x 1 FXIO_D x Logic Output to FXIO_D x 4 0 0 0 0 0 SHIFTBUFi 0 0 0 0 0 1 SHIFTBUFi 1 0 0 0 1 0 SHIFTBUFi 2 0 0 0 1 1 SHIFTBUF...

Page 571: ...lock or select output or a PWM waveform Timers can be configured to enable in response to a trigger pin or shifter condition decrement always or only on a trigger or pin edge reset in response to a tr...

Page 572: ...output will toggle the lower 8 bit counter register will reload from the compare register and the upper 8 bit counter will decrement For 8 bit PWM mode the lower 8 bit counter will only decrement when...

Page 573: ...hile the timer is in the stop state condition If there is no configured edge between the timer disable and the next rising edge of the shift clock then the final store and verify do not occur 22 3 3 P...

Page 574: ...red as a pin input the input signal is first synchronized to the FlexIO clock before the signal is used by a timer or shifter This introduces a small latency of between 0 5 to 1 5 FlexIO clock cycles...

Page 575: ...ered allowing an address mark bit or additional stop bit to remain undisturbed FlexIO does not support automatic insertion of parity bits Table 22 4 UART Transmit Configuration Register Value Comments...

Page 576: ...h Break characters will cause the error flag to set and the shifter buffer register will return 0x00 FlexIO does not support automatic verification of parity bits Table 22 5 UART Receiver Configuratio...

Page 577: ...by 4 of the FlexIO clock Set TIMCMP 15 8 number of bits x 2 1 Set TIMCMP 7 0 baud rate divider 2 1 TIMCFGn 0x0204_2522 Configure start bit stop bit enable on pin posedge with trigger low and disable...

Page 578: ...FG n 1 0x0000_0000 Start and stop bit disabled SHIFTCTL n 1 0x0000_0101 Configure receive using Timer 0 on posedge of clock with input data on Pin 1 TIMCMPn 0x0000_3F01 Configure 32 bit transfer with...

Page 579: ...k Set TIMCMP 15 8 number of bits x 2 1 Set TIMCMP 7 0 baud rate divider 2 1 TIMCFGn 0x0100_2222 Configure start bit stop bit enable on trigger high and disable on compare initial clock state is logic...

Page 580: ...lock cycles so the maximum baud rate is divide by 6 of the FlexIO clock frequency Table 22 9 SPI Slave CPHA 0 Configuration Register Value Comments SHIFTCFGn 0x0000_0000 Start and stop bit disabled SH...

Page 581: ...shift clock with input data on Pin 1 TIMCMPn 0x0000_003F Configure 32 bit transfer Set TIMCMP 15 0 number of bits x 2 1 TIMCFGn 0x0120_6602 Configure start bit enable on trigger rising edge disable on...

Page 582: ...ceiving and the receive shifter returns the data actually present on the SDA pin The transmit shifter will load 1 additional word on the last falling edge of SCL pin this word should be 0x00 if genera...

Page 583: ...e SCL open drain with Shifter 0 flag as the inverted trigger TIMCMP n 1 0x0000_000F Configure 8 bit transfer Set TIMCMP 15 0 number of bits x 2 1 TIMCFG n 1 0x0020_1112 Enable when Timer 0 is enabled...

Page 584: ...er 0 on falling edge of clock with input data on Pin 1 TIMCMPn 0x0000_3F01 Configure 32 bit transfer with baud rate of divide by 4 of the FlexIO clock Set TIMCMP 15 8 number of bits x 2 1 Set TIMCMP 7...

Page 585: ...e of I2S slave is max 2 5 cycles because there is a maximum 1 5 cycle delay on the clock synchronization plus 1 cycle to output the data Table 22 13 I2S Slave Configuration Register Value Comments SHI...

Page 586: ...ace Camera Interface can be supported using one Timer one or more Shifters and multiple Pins Multiple transfers can be supported using DMA controller The example below describes FlexIO configuration f...

Page 587: ...th GPIO FlexIO is able to drive these interfaces using one Timer and one Shifter although additional Shifters could be used to support large transfers via the DMA controller The configuration below pr...

Page 588: ...Timer 0 on negedge of clock with data input from FXIO_D 15 0 TIMCMP0 0x0000_0101 1 beat 0x0000_1F01 16 beats Configure 1 or 16 beat transfer with baud rate of divide by 4 of the FlexIO clock Set TIMC...

Page 589: ...al state machine example to illustrate the flexibility allowed when using Shifter state mode In this example FlexIO waits for the FXIO_D 2 pin to assert and then drives a complementary square wave out...

Page 590: ...te0 if FXIO_D 2 0 State1 if FXIO_D 2 1 SHIFTCTL1 0x0000_0206 Configure for State mode using FXIO_D 4 2 as inputs to select next state and Timer0 output high to trigger next state SHIFTBUF1 0x0140_8408...

Page 591: ...Configure timer always enabled TIMCTL0 0x0000_0003 Configure single 16 bit counter TIMCFG1 0x0010_7600 Configure timer enabled on trigger rising edge disabled on trigger falling edge decrement on trig...

Page 592: ...Application Information K32 L2A Reference Manual Rev 2 01 2020 592 NXP Semiconductors...

Page 593: ...able shows the supported read write operations Flash memory type Read Write Program flash memory 8 bit 16 bit and 32 bit reads 1 1 A write operation to program flash memory results in a bus error The...

Page 594: ...or data Enable and invalidation controls for cache Read accesses that hit a valid speculation or cache entry return the read data with no wait states 23 2 Modes of operation The FMC only operates when...

Page 595: ...Mid level state is execute only Unsecure state is where no access control states are set Features Lightweight access control logic for on chip flash memory Flash address space divided into 32 or 64 eq...

Page 596: ...ode SAn 0 The flash is released from reset early while the core continues to be held in reset The FMU captures the NVM access control information in internal registers The FMU ANDs the multiple execut...

Page 597: ...lash size 64 Program flash size 64 Program flash size 64 Program flash size 64 SA0 XA0 0x0000_0000 SA1 XA1 SA2 XA2 SA3 XA3 SA61 XA61 SA63 XA63 SA62 XA62 Program flash Last program flash address Access...

Page 598: ...he PGMCHK on a segment that has been configured as execute only The Flash Protection Violation flag is set if an attempt is made to execute PGMCHK command on an execute only address Erase Flash Sector...

Page 599: ...After the first valid instruction fetch the FAC logic follows normal checks 23 5 2 4 Software considerations There are software considerations that need to be communicated to tool and library vendors...

Page 600: ...acc i 1 extract sacc bit for this segment xacc_flag xacc i 1 extract xacc bit for this segment create a 4 tuple concatenating the 2 bit protection field sacc xacc flags switch hprot 3 2 sacc_flag 1 xa...

Page 601: ...ng available on chip flash The device continues to support the end user with standard security features that further limit external access to flash resources 23 6 Initialization and application inform...

Page 602: ...Initialization and application information K32 L2A Reference Manual Rev 2 01 2020 602 NXP Semiconductors...

Page 603: ...nly move bits from the 1 state erased to the 0 state programmed Only the erase operation restores bits from 0 to 1 bits cannot be programmed from a 0 to a 1 CAUTION A flash memory location must be in...

Page 604: ...built in program and erase algorithms with verify Read access to one program flash block is possible while programming or erasing data in the other program flash block 24 1 1 2 Other Flash Memory Modu...

Page 605: ...sh Common Command Object A group of flash registers that are used to pass command address data and any associated parameters to the memory controller in the flash memory module Flash block A macro wit...

Page 606: ...yte address 2 0 000 Program flash The program flash memory provides nonvolatile storage for vectors and code store Program flash Sector The smallest portion of the program flash memory consecutive add...

Page 607: ...uring the Chip Using Backdoor Key Access 0x0_0408 0x0_040B 4 Program flash protection bytes Refer to the description of the Program Flash Protection Registers FPROT0 3 0x0_040F 1 Reserved 0x0_040E 1 R...

Page 608: ...e Field in the program flash IFR provides 96 bytes of user data storage separate from the program flash main array The user can program the Program Once Field one time only as there is no program flas...

Page 609: ...ol and status registers NOTE While a command is running FSTAT CCIF 0 register writes are not accepted to any register except FCNFG and FSTAT The no write rule is relaxed during the start up reset sequ...

Page 610: ...00h 24 3 4 5 616 4002_000E Flash Common Command Object Registers FTFA_FCCOB9 8 R W 00h 24 3 4 5 616 4002_000F Flash Common Command Object Registers FTFA_FCCOB8 8 R W 00h 24 3 4 5 616 4002_0010 Program...

Page 611: ...TFA_SACCL2 8 R Undefined 24 3 4 8 620 4002_0026 Supervisor only Access Registers FTFA_SACCL1 8 R Undefined 24 3 4 8 620 4002_0027 Supervisor only Access Registers FTFA_SACCL0 8 R Undefined 24 3 4 8 62...

Page 612: ...h Access Error Flag Indicates an illegal access has occurred to a flash memory resource caused by a violation of the command write sequence or issuing an illegal flash command While ACCERR is set the...

Page 613: ...interrupt enabled An interrupt request is generated whenever the FSTAT CCIF flag is set 6 RDCOLLIE Read Collision Error Interrupt Enable Controls interrupt generation when a flash memory read collisio...

Page 614: ...ead only field is reserved and always has the value 0 24 3 4 3 Flash Security Register FTFA_FSEC This read only register holds all bits associated with the security of the MCU and flash memory module...

Page 615: ...ory access granted SEC Flash Security Defines the security state of the MCU In the secure state the MCU limits access to flash memory module resources The limitations are defined per device and are de...

Page 616: ...that compose the FCCOB data set can be written in any order but you must provide all needed values which vary from command to command First set up all required FCCOB fields and then initiate the comm...

Page 617: ...words 2 bytes or aligned longwords 4 bytes 24 3 4 6 Program Flash Protection Registers FTFA_FPROTn The FPROT registers define which program flash regions are protected from program and erase operation...

Page 618: ...gion can be protected from program and erase operations by setting the associated PROT bit In NVM Normal mode The protection can only be increased meaning that currently unprotected memory can be prot...

Page 619: ...size Execute only access register Program flash execute only access bits XACCH0 XA 63 56 XACCH1 XA 55 48 XACCH2 XA 47 40 XACCH3 XA 39 32 XACCL0 XA 31 24 XACCL1 XA 23 16 XACCL2 XA 15 8 XACCL3 XA 7 0 D...

Page 620: ...visor access The eight SACC registers allow up to 64 restricted segments of equal memory size Supervisor only access register Program flash supervisor only access bits SACCH0 SA 63 56 SACCH1 SA 55 48...

Page 621: ...ess control 0 Associated segment is accessible in supervisor mode only 1 Associated segment is accessible in user or supervisor mode 24 3 4 9 Flash Access Segment Size Register FTFA_FACSS The flash ac...

Page 622: ...in the register are read only The contents of this register are loaded during the reset sequence Address 4002_0000h base 2Bh offset 4002_002Bh Bit 7 6 5 4 3 2 1 0 Read NUMSG Write Reset x x x x x x x...

Page 623: ...h Last program flash address Figure 24 2 Program flash protection NOTE Flash protection features are discussed further in AN4507 Using the Kinetis Security and Flash Protection Features Not all featur...

Page 624: ...ure 24 3 Program flash execute only access control 256KB or 512KB of program flash FTFA_SACC For 2n program flash sizes greater than 128KB eight registers control 64 segments of the program flash memo...

Page 625: ...the MCU level Some devices also generate a bus error response as a result of a Read Collision Error event See the chip configuration information to determine if a bus error response is also supported...

Page 626: ...ss to execute a flash memory read The MCU must not read from the flash memory while commands are running as evidenced by CCIF 0 on that block Read data cannot be guaranteed from a flash block while an...

Page 627: ...memory module performs various checks on the command FCCOB content and continues with command execution if all requirements are fulfilled Before launching a command the ACCERR and FPVIOL bits in the F...

Page 628: ...ually access errors suggest that the command was not set up with valid parameters in the FCCOB register group Program and erase commands also check the address to determine if the operation is request...

Page 629: ...ster no yes no yes Previous command complete no CCIF 1 yes START CCIF 1 Read FSTAT register no yes Bit Polling for Command Completion Check Figure 24 5 Generic flash command write sequence flowchart 2...

Page 630: ...program flash sector 0x40 Read 1s All Blocks Verify that all program flash blocks are erased then release MCU security 0x41 Read Once IFR Read 4 bytes of a dedicated 64 byte field in the program flas...

Page 631: ...de The following table shows the flash commands that can be executed in each flash operating mode Table 24 2 Flash Commands by Mode FCMD Command NVM Normal NVM Special Unsecure Secure MEEN 10 Unsecure...

Page 632: ...ons at tighter tolerances than a normal read These non standard read levels are applied only during the command execution Basic flash array reads use the standard un margined read reference level Only...

Page 633: ...e initial factory programming 24 4 11 Flash Command Description This section describes all flash commands that can be launched by a command write sequence The flash memory module sets the FSTAT ACCERR...

Page 634: ...rogram flash block Table 24 5 Margin Level Choices for Read 1s Block Read Margin Choice Margin Level Description 0x00 Use the normal read level for 1s 0x01 Apply the User margin to the normal read 1 l...

Page 635: ...Section operation completes Table 24 8 Margin Level Choices for Read 1s Section Read Margin Choice Margin Level Description 0x00 Use the normal read level for 1s 0x01 Apply the User margin to the nor...

Page 636: ...STAT0 is set FSTAT CCIF is set after the Program Check operation completes The supplied address must be longword aligned the lowest two bits of the byte address must be 00 Byte 3 data is written to th...

Page 637: ...ory resources available include program flash IFR space and the Version ID field Each resource is assigned a select code as shown in Table 24 14 Table 24 13 Read Resource Command FCCOB Requirements FC...

Page 638: ...rd aligned FSTAT ACCERR 24 4 11 5 Program Longword Command The Program Longword command programs four previously erased bytes in the program flash memory using an embedded algorithm CAUTION A flash me...

Page 639: ...ogram Longword Command Error Handling Error Condition Error Bit Command not available in current mode security FSTAT ACCERR An invalid flash address is supplied FSTAT ACCERR Flash address is not longw...

Page 640: ...FSTAT FPVIOL Any errors have been encountered during the verify operation1 FSTAT MGSTAT0 1 User margin read may be run using the Read 1s Block command to verify all bits are erased 24 4 11 7 Erase Fla...

Page 641: ...writes to flash registers are ignored except for writes to the FSTAT and FCNFG registers If an Erase Flash Sector operation effectively completes before the flash memory module detects that a suspend...

Page 642: ...ion by clearing the ERSSUSP bit prior to clearing CCIF for the next command launch When a suspended operation is aborted the flash memory module starts the new command using the new FCCOB contents Not...

Page 643: ...ERSSUSP Execute Yes DONE No ERSSUSP 1 Save Erase Algo Set CCIF No Yes Start New Resume Erase No Abort User Cmd Interrupt Suspend Set SUSPACK 1 ERSSCR Suspended Command Initiation Yes No Yes Yes ERSSCR...

Page 644: ...y is released by setting the FSEC SEC field to the unsecure state The security byte in the flash configuration field see Flash Configuration Field Description remains unaffected by the Read 1s All Blo...

Page 645: ...Not used 3 Not used Returned Values 4 Program Once byte 0 value 5 Program Once byte 1 value 6 Program Once byte 2 value 7 Program Once byte 3 value 8 Program Once byte 4 value index 0x10 0x13 9 Progra...

Page 646: ...mand These records can be reprogrammed since the program flash erasable IFR can be erased using the Erase All Blocks command and Erase All Blocks Unsecure command Table 24 27 Program Once Command FCCO...

Page 647: ...COB Number FCCOB Contents 7 0 0 0x44 ERSALL After clearing CCIF to launch the Erase All Blocks command the flash memory module erases all program flash memory and the program flash erasable IFR space...

Page 648: ...flash erasable IFR space regardless of the protection settings If the post erase verify passes access control determined by the contents of the FXACC registers is disabled and the routine then releas...

Page 649: ...curity is released If the backdoor keys do not match security is not released and all future attempts to execute the Verify Backdoor Access Key command are immediately aborted and the FSTAT ACCERR bit...

Page 650: ...rase or program verify fails the FSTAT MGSTAT0 bit is set The CCIF flag is set after the Erase All Blocks Unsecure operation completes Access control determined by the contents of the FXACC registers...

Page 651: ...until the next reset or after programming any of the execute only segments the Read 1s All Execute only Segments command is executed and fails with the FSTAT MGSTAT0 bit set If the read fails i e all...

Page 652: ...XA controlled segment is protected If the erase verify fails the FSTAT MGSTAT0 bit is set The CCIF flag is set after the Erase All Execute only Segments operation completes Access control determined b...

Page 653: ...7 Using the Kinetis Security and Flash Protection Features Note that not all features described in the application note are available on this device Table 24 40 FSEC register fields FSEC field Descrip...

Page 654: ...the Verify Backdoor Access Key command is active program flash memory is not available for read access and returns invalid data The user code stored in the program flash memory must have a method of r...

Page 655: ...lash memory module executes a sequence which establishes initial values for the flash block configuration parameters FPROT FOPT FSEC FXACC FSACC and FACNFG registers FSTAT CCIF is cleared throughout t...

Page 656: ...Functional Description K32 L2A Reference Manual Rev 2 01 2020 656 NXP Semiconductors...

Page 657: ...ide up to 32 additional interrupt sources which can be logically OR d or ANDed The Interrupt Multiplexer INTMUX routes the interrupt sources to the interrupt outputs 25 1 2 Features INTMUX features Su...

Page 658: ...el 2 channel N INTMUX Figure 25 1 INTMUX Block diagram N Interrupt Channel Instance Number N 3 X Interrupt Source Number for each channel X 32 25 2 Memory Map and register definition This section incl...

Page 659: ..._4084 Channel n Vector Number Register INTMUX0_CH2_VEC 32 R 0000_0000h 25 2 2 660 4002_4090 Channel n Interrupt Enable Register INTMUX0_CH2_IER_31_0 32 R W 0000_0000h 25 2 3 661 4002_40A0 Channel n In...

Page 660: ...rved 11 Reserved 3 2 Reserved This field is reserved This read only field is reserved and always has the value 0 1 AND Logic AND This bit used to Logic AND or Logic OR all enabled interrupt inputs of...

Page 661: ...r INTMUXx_CHn_IER_31_0 Address 4002_4000h base 10h offset 64d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R INTE W Reset 0 0 0 0 0 0 0...

Page 662: ...el Software resets can also be performed on a given channel See the chip specific Interrupt section for more information regarding the interrupt vectors and sources 25 3 1 Configuring Output Channels...

Page 663: ...field starts at bit 2 of the CHn_VEC register so reading the register as a whole will return the VECN field multiplied by 4 This is the offset in bytes of the active source vector from the start of th...

Page 664: ...Functional Description K32 L2A Reference Manual Rev 2 01 2020 664 NXP Semiconductors...

Page 665: ...can be individually enabled The RESET pin is an additional source for triggering an exit from low leakage power modes and causes the MCU to exit both LLS and VLLS through a reset flow The LLWU module...

Page 666: ...SO 26 1 2 1 LLS mode Wake up events due to external pin inputs LLWU_Px and internal module interrupt inputs LLWU_MxIF result in an interrupt flow when exiting LLS Wake up events due to internal module...

Page 667: ...26 1 2 4 Debug mode When the chip is in Debug mode and then enters LLS or a VLLSx mode no debug logic works in the fully functional low leakage mode Upon an exit from the LLS or VLLSx mode the LLWU b...

Page 668: ...Synchronizer Synchronizer Edge detect Edge detect Pin filter 2 wakeup occurred FILT2 FILTSEL FILT1 FILTSEL FILT2 FILTE Module0 DMA Request LLWU_M0DR WUDE0 Module7 DMA Request LLWU_M7DR WUDE7 DMA flow...

Page 669: ...Wake up pin filter enable registers NOTE The LLWU registers can be written only in supervisor mode Write accesses in user mode are blocked and will result in a bus error Registers for Pin Module sour...

Page 670: ...F 32 R 0000_0000h 26 3 8 686 4006_1030 LLWU Pin Filter register LLWU_FILT 32 R W 0000_0000h 26 3 9 688 26 3 1 Version ID Register LLWU_VERID Address 4006_1000h base 0h offset 4006_1000h Bit 31 30 29 2...

Page 671: ...register LLWU_PE1 LLWU_PE1 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P15 LLWU_P0 NOTE This register is reset on Chip Reset not VLLS and by re...

Page 672: ...etection 25 24 WUPE12 Wakeup Pin Enable For LLWU_P12 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin enabled with risi...

Page 673: ...wakeup pin 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabl...

Page 674: ...ection WUPE0 Wakeup Pin Enable For LLWU_P0 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge de...

Page 675: ...akeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 25 24 WUPE28 Wake...

Page 676: ...etection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 13 12 WUPE22 Wakeup Pin Enable For LLWU_P22 Enables and configures the edge d...

Page 677: ...put pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detect...

Page 678: ...urce input 0 Internal module flag not used as wakeup source 1 Internal module flag used as wakeup source 5 WUME5 Wakeup Module Enable For Module 5 Enables an internal module as a wakeup source input 0...

Page 679: ...A Enable register LLWU_DE LLWU_DE contains the bits to enable an internal module DMA request as a wakeup source for inputs LLWU_M7DR LLWU_M0DR NOTE This register is reset on Chip Reset not VLLS and by...

Page 680: ...akeup source 0 Internal module request not used as a DMA wakeup source 1 Internal module request used as a DMA wakeup source 3 WUDE3 DMA Wakeup Enable For Module 3 Enables an internal module as a DMA...

Page 681: ...006_1020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R WUF31 WUF30 WUF29 WUF28 WUF27 WUF26 WUF25 WUF24 WUF23 WUF22 WUF21 WUF20 WUF19 WUF18 WUF17 WUF16 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1...

Page 682: ...pin was a source of exiting a low leakage power mode To clear the flag write a one to WUF27 0 LLWU_P27 input was not a wakeup source 1 LLWU_P27 input was a wakeup source 26 WUF26 Wakeup Flag For LLWU...

Page 683: ...F20 0 LLWU_P20 input was not a wakeup source 1 LLWU_P20 input was a wakeup source 19 WUF19 Wakeup Flag For LLWU_P19 Indicates that an enabled external wakeup pin was a source of exiting a low leakage...

Page 684: ...Flag For LLWU_P12 Indicates that an enabled external wakeup pin was a source of exiting a low leakage power mode To clear the flag write a one to WUF12 0 LLWU_P12 input was not a wakeup source 1 LLWU_...

Page 685: ...n was a source of exiting a low leakage power mode To clear the flag write a one to WUF5 0 LLWU_P5 input was not a wakeup source 1 LLWU_P5 input was a wakeup source 4 WUF4 Wakeup Flag For LLWU_P4 Indi...

Page 686: ...mode For LLS this is the source causing the CPU interrupt flow For VLLS this is the source causing the MCU reset flow For internal peripherals that are capable of running in a low leakage power mode s...

Page 687: ...6 input was not a wakeup source 1 Module 6 input was a wakeup source 5 MWUF5 Wakeup flag For module 5 Indicates that an enabled internal peripheral was a source of exiting a low leakage power mode To...

Page 688: ...Indicates that an enabled internal peripheral was a source of exiting a low leakage power mode To clear the flag follow the internal peripheral flag clearing mechanism 0 Module 0 input was not a wake...

Page 689: ...ed 28 24 FILTSEL4 Filter 4 Pin Select Selects 1 of the wakeup pins to be muxed into filter 4 00000 Select LLWU_P0 for filter 11111 Select LLWU_P31 for filter 23 FILTF3 Filter 3 Flag Indicates that the...

Page 690: ...elects 1 of the wakeup pins to be muxed into filter 2 00000 Select LLWU_P0 for filter 11111 Select LLWU_P31 for filter 7 FILTF1 Filter 1 Flag Indicates that the filtered external wakeup pin selected b...

Page 691: ...up to 5 cycles of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled Four wakeup detect filters are available for selected external pins...

Page 692: ...by software before entering LLS or VLLSx mode to avoid an immediate exit from the mode Flags associated with external input pins filtered and unfiltered must also be cleared by software prior to entr...

Page 693: ...LPI2C module also complies with the System Management Bus SMBus Specification version 2 27 1 2 Features The LPI2C supports the following features of the I2C specification Standard Fast Fast and Ultra...

Page 694: ...nd command word errors Supports configurable bus idle timeout and pin stuck low timeout The LPI2C slave supports the following features Separate I2C slave registers to minimize software overhead due t...

Page 695: ...ss Configuration Registers Slave Logic SDAS SCLS Glitch Filter Bus Clock External Clock Functional Clock Clock Domains Command TX FIFO Figure 27 1 LPI2C block diagram 27 1 4 Modes of operation The LPI...

Page 696: ...the SDA input pin I O HREQ Host request can initiate an LPI2C master transfer if asserted and the I2C bus is idle I SCLS Secondary I2C clock line In 4 wire mode this is the SCL output pin If LPI2C ma...

Page 697: ...000_0000h 27 2 14 715 4004_205C Master FIFO Status Register LPI2C2_MFSR 32 R 0000_0000h 27 2 15 715 4004_2060 Master Transmit Data Register LPI2C2_MTDR 32 W 0000_0000h 27 2 16 716 4004_2070 Master Rec...

Page 698: ...0C_0048 Master Clock Configuration Register 0 LPI2C0_MCCR0 32 R W 0000_0000h 27 2 12 713 400C_0050 Master Clock Configuration Register 1 LPI2C0_MCCR1 32 R W 0000_0000h 27 2 13 714 400C_0058 Master FIF...

Page 699: ...figuration Register 3 LPI2C1_MCFGR3 32 R W 0000_0000h 27 2 10 712 400C_1040 Master Data Match Register LPI2C1_MDMR 32 R W 0000_0000h 27 2 11 712 400C_1048 Master Clock Configuration Register 0 LPI2C1_...

Page 700: ...ess Base address 0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MAJOR MINOR FEATURE W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 701: ...d only field is reserved and always has the value 0 15 12 Reserved This field is reserved This read only field is reserved and always has the value 0 11 8 MRXFIFO Master Receive FIFO Size The number o...

Page 702: ...eserved This read only field is reserved and always has the value 0 9 RRF Reset Receive FIFO 0 No effect 1 Receive FIFO is reset 8 RTF Reset Transmit FIFO 0 No effect 1 Transmit FIFO is reset 7 4 Rese...

Page 703: ...W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 DMF PLTF FEF ALF NDF SDF EPF 0 RDF TDF W w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 LPI2Cx_...

Page 704: ...the LPI2C master transmits a logic one and detects a logic zero on the I2C bus or if it detects a START or STOP condition while it is transmitting data When this flag sets the LPI2C master will relea...

Page 705: ...27 2 5 Master Interrupt Enable Register LPI2Cx_MIER Address Base address 18h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 1...

Page 706: ...ed 1 Interrupt enabled 9 SDIE STOP Detect Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 8 EPIE End Packet Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 7 2 Reserved This field...

Page 707: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPI2Cx_MDER field descriptions Field Description 31 2 Reserved This field is reserved This read only field is reserved and always has the value 0 1 RDDE Receive Data DMA E...

Page 708: ...arded unless the RMF is set 8 CIRFIFO Circular FIFO Enable When enabled the transmit FIFO read pointer is saved to a temporary register The transmit FIFO will be emptied as normal but once the LPI2C m...

Page 709: ...16 R 0 PINCFG 0 MATCFG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 TIMECFG IGNACK AUTOSTOP 0 PRESCALE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPI2Cx_MCFGR1 f...

Page 710: ...IMECFG Timeout Configuration 0 Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout 1 Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the config...

Page 711: ...cycle count is not affected by the PRESCALE configuration and is automatically bypassed in High Speed mode 23 20 Reserved This field is reserved This read only field is reserved and always has the val...

Page 712: ...Reserved This field is reserved This read only field is reserved and always has the value 0 27 2 11 Master Data Match Register LPI2Cx_MDMR Address Base address 40h offset Bit 31 30 29 28 27 26 25 24...

Page 713: ...ter as the setup and hold time for a repeated START condition and setup time for a STOP condition The setup time is extended by the time it takes to detect a rising edge on the external SCL pin Ignori...

Page 714: ...e value 0 21 16 SETHOLD Setup Hold Delay Minimum number of cycles minus one that is used by the master as the setup and hold time for a repeated START condition and setup time for a STOP condition The...

Page 715: ...ransmit Data Flag is set whenever the number of words in the transmit FIFO is equal or less than TXWATER Writing a value equal or greater than the FIFO size will be truncated 27 2 15 Master FIFO Statu...

Page 716: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPI2Cx_MTDR field descriptions Field Description 31 11 Reserved This field is reserved 10 8 CMD Command Data 000 Transmit DATA 7 0 001 Receive DATA 7 0 1 bytes 010...

Page 717: ...his read only field is reserved and always has the value 0 14 RXEMPTY RX Empty 0 Receive FIFO is not empty 1 Receive FIFO is empty 13 8 Reserved This field is reserved This read only field is reserved...

Page 718: ...the value 0 9 RRF Reset Receive FIFO 0 No effect 1 Receive Data Register is now empty 8 RTF Reset Transmit FIFO 0 No effect 1 Transmit Data Register is now empty 7 6 Reserved This field is reserved Th...

Page 719: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 BBF SBF 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SARF GCF AM1F AM0F FEF BEF SDF RSF 0 TAF AVF RDF TDF...

Page 720: ...lag is cleared by reading the Address Status Register This flag cannot generate an asynchronous wakeup 0 Have not received ADDR1 or ADDR0 ADDR1 range matching address 1 Have received ADDR1 or ADDR0 AD...

Page 721: ...eared by writing the transmit ACK register 0 Transmit ACK NACK is not required 1 Transmit ACK NACK is required 2 AVF Address Valid Flag This flag is cleared by reading the address status register When...

Page 722: ...s has the value 0 15 SARIE SMBus Alert Response Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 14 GCIE General Call Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 13 AM1F Address...

Page 723: ...e 0 Interrupt disabled 1 Interrupt enabled 1 RDIE Receive Data Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 0 TDIE Transmit Data Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled...

Page 724: ...A request enabled 27 2 22 Slave Configuration Register 1 LPI2Cx_SCFGR1 The SCFGR1 should only be written when the I2C Slave is disabled Address Base address 124h offset Bit 31 30 29 28 27 26 25 24 23...

Page 725: ...data and clear the receive data flag 1 Reading the receive data register when the address valid flag is set will return the address status register and clear the address valid flag Reading the receiv...

Page 726: ...lock stretching occurs following the 9th bit and is therefore compatible with high speed mode 0 Clock stretching disabled 1 Clock stretching enabled 1 RXSTALL RX SCL Stall Enables SCL clock stretching...

Page 727: ...glitch filter cycle count is not affected by the PRESCALE configuration and is disabled in high speed mode 15 14 Reserved This field is reserved This read only field is reserved and always has the va...

Page 728: ...ld is reserved This read only field is reserved and always has the value 0 27 2 25 Slave Address Status Register LPI2Cx_SASR Address Base address 150h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 729: ...This read only field is reserved and always has the value 0 0 TXNACK Transmit NACK When NACKSTALL is set must be written once for each matching address byte and each received word Can also be written...

Page 730: ...0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SOF RXEMPTY 0 DATA W Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPI2Cx_SRDR field descriptions Field Description 31 16 Reserved This field is reserved This re...

Page 731: ...l filter and data hold time configurations The LPI2C master divides the functional clock by a prescaler and the resulting frequency must be at least eight times faster than the I2C bus bandwidth 27 3...

Page 732: ...reset all slave logic and registers to their default state except for the SCR itself 27 3 1 6 FIFO reset The LPI2C master implements write only control bits that resets the transmit FIFO MCR RTF and...

Page 733: ...mple hs mode master code must be followed by a STOP or repeated START condition 27 3 2 2 Master Operation Whenever the LPI2C is enabled it monitors the I2C bus to detect when the I2C bus is idle MSR B...

Page 734: ...t one of two bytes or against a masked data byte The data match function can also be configured to compare only the first one or two received data words since the last repeated START condition Receive...

Page 735: ...two plus the pin input digital filter setting which are configured separately for SCL and SDA divided by the prescaler since the pin input digital filters are not affected by the prescaler setting Th...

Page 736: ...5 Mbps 0x0 0x0 0x0 0x02 0x05 0x03 0x01 The formula to calculate number of cycles per bit is as follows Baud rate divide CLKLO CLKHI 2 2 PRESCALER ROUNDDOWN 2 FILTSCL 2 PRESCALER This assumes SCL will...

Page 737: ...source pull up required in the I2C specification The LPI2C master also supports the output only push pull function required for I2C ultra fast mode using the LPI2C_SDA and LPI2C_SCL pins Support for...

Page 738: ...ouble buffered and only update during a slave transmit and slave receive transfer respectively The slave address that was received can be configured to be read from either the receive data register fo...

Page 739: ...A update SCL hold time when clock stretching is enabled to increase setup time when sampling SDA externally SCL glitch filter time SDA glitch filter time The LPI2C slave imposes the following restrict...

Page 740: ...I2C master interrupt and LPI2C master transmit receive DMA requests Table 27 4 Master Interrupts and DMA Requests Flag Description Interrupt DMA Request Low Power Wakeup TDF Data can be written to tra...

Page 741: ...LPI2C master is busy transmitting receiving data N N N BBF LPI2C master is enabled and activity detected on I2C bus but STOP condition has not been detected and bus idle timeout if enabled has not oc...

Page 742: ...F Transmit data underrun receive data overrun or address status overrun when RXCFG 1 This flag can only set when clock stretching is disabled Y N Y AM0F Slave detected address match with ADDR0 field Y...

Page 743: ...Trigger The LPI2C slave generates an output trigger that can be connected to other peripherals on the device The slave output trigger asserts on both a Repeated START or STOP condition that occurs fol...

Page 744: ...Functional description K32 L2A Reference Manual Rev 2 01 2020 744 NXP Semiconductors...

Page 745: ...1 clock cycle delayed of the pre trigger pulse Each timer channel start reload and restart can be controlled via control bits The timer can be configured to always decrement or decrement on selected t...

Page 746: ...o all Timer channels Channel Registers Access Synchronizer Counter Value Timeout Load Enable Sync ed External Triggers per channel Timer Channel n Figure 28 1 Top Level Block Diagram 28 2 Modes of ope...

Page 747: ...0h 28 3 5 751 4003_0014 Set Timer Enable Register LPIT0_SETTEN 32 R W 0000_0000h 28 3 6 752 4003_0018 Clear Timer Enable Register LPIT0_CLRTEN 32 W always reads 0 0000_0000h 28 3 7 754 4003_0020 Timer...

Page 748: ...3 2 Parameter Register LPITx_PARAM This register provides details on the parameter settings that were used while including this module in the device Address 4003_0000h base 4h offset 4003_0004h Bit 3...

Page 749: ...ows the timer channels to be stopped when the device enters the Debug mode 0 Timer channels are stopped in Debug mode 1 Timer channels continue to run in Debug mode 2 DOZE_EN DOZE Mode Enable Bit Allo...

Page 750: ...w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPITx_MSR field descriptions Field Description 31 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 TIF3 Ch...

Page 751: ...Description 31 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 TIE3 Channel 3 Timer Interrupt Enable Enables interrupt generation when this bit is set...

Page 752: ...h offset 4003_0014h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SET_T_EN_3 SET_T_EN_2 SET_T_EN_1 SET_T...

Page 753: ...n be used in addition to T_EN bit in TCTRL1 register Writing a 0 will not disable the counter This bit will be cleared when T_EN bit in TCTRL1 is set to 0 or 1 is written to the CLR_T_EN_1 bit in CLRT...

Page 754: ...e Writing a 1 to this bit will disable the timer channel 3 This bit can be used in addition to T_EN bit in TCTRL3 register Writing a 1 will not enable the counter This bit is self clearing and will al...

Page 755: ...sserts Address 4003_0000h base 20h offset 16d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TMR_VAL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 756: ...CVALn field descriptions Field Description TMR_CUR_VAL Current Timer Value Represents the current timer value if the timer is enabled 28 3 10 Timer Control Register LPITx_TCTRLn These registers contai...

Page 757: ...2 19 Reserved This field is reserved This read only field is reserved and always has the value 0 18 TROT Timer Reload On Trigger When set the LPIT timer will reload when a rising edge is detected on t...

Page 758: ...ut 0 T_EN Timer Enable Enables or disables the Timer Channel 0 Timer Channel is disabled 1 Timer Channel is enabled 28 4 Functional description 28 4 1 Initialization The following steps can be used to...

Page 759: ...iting 1 to them 28 4 2 Timer Modes The timer mode is configured by setting an appropriate value in the MODE bits in TCTRLn register The timer modes supported are 32 bit Periodic Counter In this mode t...

Page 760: ...ter stops on TIF assertion Requires trigger if TSOT 1 or T_EN rising edge if TSOT 0 to reload and decrement If TSOI 0 counter does not stop after timeout If TROT 1 counter is loaded on each trigger el...

Page 761: ...The channels are chained by setting the CHAIN bit in corresponding channel s TCTRLn register When a channel is chained that channel s timer decrements on previous channel s timeout pulse irrespective...

Page 762: ...Functional description K32 L2A Reference Manual Rev 2 01 2020 762 NXP Semiconductors...

Page 763: ...I can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses 29 1 2 Features The LPSPI supports...

Page 764: ...e Chip mode LPSPI Operation Run Normal operation Stop Wait Can continue operating if the Doze Enable bit CR DOZEN is set and the LPSPI is using an external or internal clock source which remains opera...

Page 765: ...configured as serial data input signal Used as data pin 0 in quad data and dual data transfers I O SIN DATA 1 Serial Data Input Can be configured as serial data output signal Used as data pin 1 in qu...

Page 766: ...768 400B_C010 Control Register LPSPI0_CR 32 R W 0000_0000h 29 2 3 769 400B_C014 Status Register LPSPI0_SR 32 R W 0000_0001h 29 2 4 770 400B_C018 Interrupt Enable Register LPSPI0_IER 32 R W 0000_0000h...

Page 767: ...9 2 10 777 400B_D040 Clock Configuration Register LPSPI1_CCR 32 R W 0000_0000h 29 2 11 778 400B_D058 FIFO Control Register LPSPI1_FCR 32 R W 0000_0000h 29 2 12 779 400B_D05C FIFO Status Register LPSPI...

Page 768: ...egister LPSPIx_PARAM Address Base address 4h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 RXFIFO TXFIFO W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 769: ...ead only field is reserved and always has the value 0 9 RRF Reset Receive FIFO 0 No effect 1 Receive FIFO is reset 8 RTF Reset Transmit FIFO 0 No effect 1 Transmit FIFO is reset 7 4 Reserved This fiel...

Page 770: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 DMF REF TEF TCF FCF WCF 0 RDF TDF W w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 LPSPIx_SR field descriptions Field Description 31 25 Reserved This...

Page 771: ...ansfer when the PCS negates 0 Frame transfer has not completed 1 Frame transfer has completed 8 WCF Word Complete Flag This flag will set when the last bit of a received word is sampled 0 Transfer wor...

Page 772: ...E Receive Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 11 TEIE Transmit Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 10 TCIE Transfer Complete Interrupt Enable 0...

Page 773: ...8 7 6 5 4 3 2 1 0 R 0 RDDE TDDE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPSPIx_DER field descriptions Field Description 31 2 Reserved This field is reserved This read only field is reserved and alway...

Page 774: ...s discarded unless the DMF is set 8 CIRFIFO Circular FIFO Enable When enabled the transmit FIFO read pointer is saved to a temporary register The transmit FIFO will be emptied as normal but once the L...

Page 775: ...UTCFG PINCFG 0 MATCFG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PCSPOL 0 NOSTALL AUTOPCS SAMPLE MASTER W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPSPIx_CFGR1...

Page 776: ...1 15 12 Reserved This field is reserved This read only field is reserved and always has the value 0 11 8 PCSPOL Peripheral Chip Select Polarity Configures the polarity of each Peripheral Chip Select p...

Page 777: ...pins 0 Slave mode 1 Master mode 29 2 9 Data Match Register 0 LPSPIx_DMR0 Address Base address 30h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MA...

Page 778: ...ion and the minimum delay is 1 cycle 15 8 DBT Delay Between Transfers Configures the delay in master mode from the PCS negation to the next PCS assertion The delay is equal to DBT 2 cycles of the LPSP...

Page 779: ...ansmit Data Flag is set whenever the number of words in the transmit FIFO is equal or less than TXWATER Writing a value equal or greater than the FIFO size will be truncated 29 2 13 FIFO Status Regist...

Page 780: ...ged before an existing frame has completed then the existing frame will terminate and the command word will then update The command word can be changed during a continuous transfer provided CONTC of t...

Page 781: ...or the transfer This field is only updated between frames 00 Transfer using LPSPI_PCS 0 01 Transfer using LPSPI_PCS 1 10 Transfer using LPSPI_PCS 2 11 Transfer using LPSPI_PCS 3 23 LSBF LSB First 0 Da...

Page 782: ...ted In master mode this bit will initiate a new transfer which cannot be aborted by another command word and the bit will be cleared by hardware at the end of the transfer 00 Normal transfer 01 Mask t...

Page 783: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W DATA Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPSPIx_TDR field descriptions Field Description DATA Transm...

Page 784: ...scriptions Field Description 31 2 Reserved This field is reserved This read only field is reserved and always has the value 0 1 RXEMPTY RX FIFO Empty 0 RX FIFO is not empty 1 RX FIFO is empty 0 SOF St...

Page 785: ...PI bus transfers in both master and slave modes If the functional clock is disabled in slave mode the LPSPI can transfer a single word before the functional clock needs to be enabled The LPSPI divides...

Page 786: ...IFO CR RRF A FIFO is empty after being reset 29 3 2 Master Mode 29 3 2 1 Transmit and Command FIFO The transmit and command FIFO is a combined FIFO that includes both transmit data and command words C...

Page 787: ...frame based on FRAMESZ configuration and the TXMSK bit will be cleared at the end of the transfer The following table describes the attributes that are controlled by the command word Table 29 2 LPSPI...

Page 788: ...PI bus transfers in either half duplex or full duplex data formats Two and four bit transfers are useful for interfacing to QuadSPI memory devices and only support half duplex data formats at least on...

Page 789: ...ta match function that can match received data against one of two words or against a masked data word The data match function can also be configured to compare only the first one or two received data...

Page 790: ...ferent words of a SPI bus transfer 0 1 cycle 255 256 cycles PCSSCK Configures the minimum delay between PCS assertion and the first SCK edge to PCSSCK 1 cycles 0 1 cycle 255 256 cycles SCKPCS Configur...

Page 791: ...static and configured by PCSPOL If PCSCFG is set then PCS 3 2 should not be selected LSBF Configures if LSB bit 0 or MSB bit 31 for a 32 bit word is transmitted received first BYSW Enables byte swap...

Page 792: ...can match received data against one of two words or against a masked data word The data match function can also be configured to compare only the first one or two received data words since the start...

Page 793: ...has been sampled Y N Y FCF Frame complete PCS has negated Y N Y TCF Transfer complete PCS has negated and transmit command FIFO is empty Y N Y TEF Transmit error flag indicates transmit command FIFO...

Page 794: ...me when PCS negates and remains asserted until PCS next asserts The word output trigger asserts at the end of each received word and remains asserted for one LPSPI_SCK period 29 3 5 2 Input Trigger Th...

Page 795: ...reset events allowing it to be used as a time of day counter 30 1 1 Features The features of the LPTMR module include 16 bit time counter or pulse counter with compare Optional interrupt can generate...

Page 796: ...30 2 LPTMR signal descriptions Table 30 2 LPTMR signal descriptions Signal I O Description LPTMR_ALTn I Pulse Counter Input pin 30 2 1 Detailed signal descriptions Table 30 3 LPTMR interface detailed...

Page 797: ...0000_0000h 30 3 2 799 400B_5008 Low Power Timer Compare Register LPTMR1_CMR 32 R W 0000_0000h 30 3 3 800 400B_500C Low Power Timer Counter Register LPTMR1_CNR 32 R W 0000_0000h 30 3 4 801 30 3 1 Low...

Page 798: ...ounter input 3 is selected 3 TPP Timer Pin Polarity Configures the polarity of the input source in Pulse Counter mode TPP must be changed only when the LPTMR is disabled 0 Pulse Counter input source i...

Page 799: ...32 glitch filter recognizes change on input pin after 16 rising clock edges 0101 Prescaler divides the prescaler clock by 64 glitch filter recognizes change on input pin after 32 rising clock edges 01...

Page 800: ...configuration details for information on the connections to these inputs 00 Prescaler glitch filter clock 0 selected 01 Prescaler glitch filter clock 1 selected 10 Prescaler glitch filter clock 2 sel...

Page 801: ...o remain operating during a low power mode then it must be disabled before entering the mode The LPTMR is reset only on global Power On Reset POR or Low Voltage Detect LVD When configuring the LPTMR r...

Page 802: ...litch filter configuration must not be altered when the LPTMR is enabled 30 4 3 1 Prescaler enabled In Time Counter mode when the prescaler is enabled the output of the prescaler directly clocks the C...

Page 803: ...y 22 to 216 prescaler clock edges When first enabled the glitch filter will wait an additional one or two prescaler clock edges due to synchronization logic 30 4 3 4 Glitch filter bypassed In Pulse Co...

Page 804: ...f the temporary register are returned on each read of the CNR When reading the CNR the bus clock must be at least two times faster than the rate at which the LPTMR counter is incrementing otherwise in...

Page 805: ...he system clock and can be used to generate a wakeup from any low power mode including the low leakage modes provided the LPTMR is enabled as a wakeup source Chapter 30 Low Power Timer LPTMR K32 L2A R...

Page 806: ...Functional description K32 L2A Reference Manual Rev 2 01 2020 806 NXP Semiconductors...

Page 807: ...y Supports operation in Stop modes Interrupt DMA or polled operation Transmit data register empty and transmission complete Receive data register full Receive overrun parity error framing error and no...

Page 808: ...configurable watermark for receive and transmit requests Option for receiver to assert request after a configurable number of idle characters if receive FIFO is not empty 31 1 2 Modes of operation 31...

Page 809: ...er is disabled or transmit direction is configured for receive data I O LPUART_RX Receive data I LPUART_CTS Clear to send I LPUART_RTS Request to send O 31 1 4 Block diagram The following figure shows...

Page 810: ...rols TxD TxD Direction TO TxD Pin Logic Loop Control To Receive Data In To TxD Pin Tx Interrupt Request LOOPS RSRC TIE TC TDRE M PT PE TCIE TE SBK T8 TXDIR Load From LPUARTx_D TXINV BRK13 ASYNCH MODUL...

Page 811: ...t value Section page 4004_6000 Version ID Register LPUART2_VERID 32 R 0400_0003h 31 2 1 813 4004_6004 Parameter Register LPUART2_PARAM 32 R See section 31 2 2 813 4004_6008 LPUART Global Register LPUA...

Page 812: ..._4024 LPUART Modem IrDA Register LPUART0_MODIR 32 R W 0000_0000h 31 2 10 829 400C_4028 LPUART FIFO Register LPUART0_FIFO 32 R W See section 31 2 11 832 400C_402C LPUART Watermark Register LPUART0_WATE...

Page 813: ...rns the feature set number 0x0001 Standard feature set 0x0003 Standard feature set with MODEM IrDA support 31 2 2 Parameter Register LPUARTx_PARAM Address Base address 4h offset Bit 31 30 29 28 27 26...

Page 814: ...cleared by software 0 Module is not reset 1 Module is reset 0 Reserved This field is reserved This read only field is reserved and always has the value 0 31 2 4 LPUART Pin Configuration Register LPUA...

Page 815: ...0 0 0 1 0 0 LPUARTx_BAUD field descriptions Field Description 31 MAEN1 Match Address Mode Enable 1 0 Normal operation 1 Enables automatic address matching or data matching mode for MATCH MA1 30 MAEN2...

Page 816: ...Data Match and Match On Off for transmitter CTS input 17 BOTHEDGE Both Edge Sampling Enables sampling of the received data on both edges of the baud rate clock effectively doubling the number of times...

Page 817: ...determines whether data characters are one or two stop bits This bit should only be changed when the transmitter and receiver are both disabled 0 One stop bit 1 Two stop bits SBR Baud Rate Modulo Div...

Page 818: ...KDIF is set when the LIN break detect circuitry is enabled and a LIN break character is detected LBKDIF is cleared by writing a 1 to it 0 No LIN break character has been detected 1 LIN break character...

Page 819: ...ng address match wakeup the IDLE bit does not get set when an address does not match 1 During receive standby state RWU 1 the IDLE bit gets set upon detection of an idle character During address match...

Page 820: ...eive buffer is greater than the number indicated by LPUART_WATER RXWATER To clear RDRF read LPUART_DATA until the number of datawords in the receive data buffer is equal to or less than the number ind...

Page 821: ...within the character To clear NF write logic one to the NF 0 No noise detected 1 Noise detected in the received character in LPUART_DATA 17 FE Framing Error Flag FE is set whenever the next character...

Page 822: ...ue such as when it is used to generate address mark or parity they it need not be written each time LPUART_DATA is written 30 R9T8 Receive Bit 9 Transmit Bit 8 R9 is the tenth data bit received when t...

Page 823: ...rupts disabled use polling 1 Hardware interrupt requested when FE is set 24 PEIE Parity Error Interrupt Enable This bit enables the parity error flag PF to generate hardware interrupt requests 0 PF in...

Page 824: ...TAT RWUID is clear NOTE RWU must be set only with CTRL WAKE 0 wakeup on idle if the channel is currently not idle This can be determined by STAT RAF If the flag is set to wake up an IDLE event and the...

Page 825: ...s enabled in Doze mode 1 LPUART is disabled in Doze mode 5 RSRC Receiver Source Select This field has no meaning or effect unless the LOOPS field is set When LOOPS is set the RSRC field determines the...

Page 826: ...er a received stop bit therefore resetting the idle count 0 Idle character bit count starts after start bit 1 Idle character bit count starts after stop bit 1 PE Parity Enable Enables hardware parity...

Page 827: ...R NOISY PARITYE FRETSC RXEMPT IDLINE 0 R9T9 R8T8 R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 W Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 LPUARTx_DATA field descriptions Field Description 31 16 Reserved This f...

Page 828: ...read is not valid 11 IDLINE Idle Line Indicates the receiver line was idle before receiving the character in DATA 9 0 Unlike the IDLE flag this bit can set for the first character received when the r...

Page 829: ...served This field is reserved This read only field is reserved and always has the value 0 MA1 Match Address 1 The MA1 and MA2 registers are compared to input data addresses when the most significant b...

Page 830: ...greater than the RXWATER configuration 7 6 Reserved This field is reserved This read only field is reserved and always has the value 0 5 TXCTSSRC Transmit CTS Source Configures the source of the CTS i...

Page 831: ...cluding the last stop bit 0 TXCTSE Transmitter clear to send enable TXCTSE controls the operation of the transmitter TXCTSE can be set independently from the state of TXRTSE and RXRTSE 0 CTS has no ef...

Page 832: ...0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 RXIDEN TXOFE RXUFE TXFE TXFIFOSIZE RXFE RXFIFOSIZE W TXFLUSH RXFLUSH Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 LPUARTx_FIFO...

Page 833: ...Transmit FIFO Buffer Flush Writing to this field causes all data that is stored in the transmit FIFO buffer to be flushed This does not affect data that is in the transmit shift register 0 No flush o...

Page 834: ...ZE Both CTRL TE and CTRL RE must be cleared prior to changing this field 0 Transmit FIFO is not enabled Buffer is depth 1 Legacy support 1 Transmit FIFO is enabled Buffer is depth indicated by TXFIFOS...

Page 835: ...in RXWATER must be set to be less than the receive FIFO buffer size as indicated by FIFO RXFIFOSIZE and FIFO RXFE and must be greater than 0 15 8 TXCOUNT Transmit Counter The value in this register i...

Page 836: ...ART baud rate generation Baud rate generation is subject to two sources of error Integer division of the asynchronous LPUART baud clock may not give the exact target frequency Synchronization with the...

Page 837: ...ginally used to gain the attention of old teletype receivers Break characters are a full character time of logic 0 10 bit to 12 bit times including the start and stop bits A longer break of 13 bit tim...

Page 838: ...es 0 0 0 1 11 bit times 0 1 0 0 11 bit times 0 1 0 1 12 bit times 0 X 1 0 12 bit times 0 X 1 1 13 bit times 1 0 0 0 13 bit times 1 0 0 1 13 bit times 1 1 0 0 14 bit times 1 1 0 1 14 bit times 1 X 1 0...

Page 839: ...ll remain asserted until the transfer is completed even if the transmitter is disabled mid way through a data transfer 31 3 2 4 Transceiver driver enable using LPUART_RTS RS 485 is a multiple drop com...

Page 840: ...he program has one full character time after LPUART_STAT RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun When a program detects that the receive data re...

Page 841: ...ter frame In the case of a framing error provided the received character was not a break character the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a ne...

Page 842: ...is mode LPUART_CTRL RWU is cleared automatically when the receiver detects a full character time of the idle line level The LPUART_CTRL M and LPUART_BAUD M10 control bit selects 8 bit to 10 bit data m...

Page 843: ...gured for data match wakeup In this mode LPUART_CTRL RWU is cleared automatically when the receiver detects a character that matches MATCH MA1 field when BAUD MAEN1 is set or that matches MATCH MA2 wh...

Page 844: ...occurs then no transfer is made to the receive data buffer and all following frames until the next idle condition are also discarded If both the LPUART_BAUD MAEN1 and LPUART_BAUD MAEN2 bits are negate...

Page 845: ...r a start bit is detected that will cause the receiver data register to be full The receiver asserts LPUART_RTS when the number of characters in the receiver data register is not full and has not dete...

Page 846: ...a 1 to the receiver If the next bit is a 0 which arrives late then a low bit is detected according to Low bit detection The value sent to the receiver is changed from 1 to a 0 Then if a noise pulse o...

Page 847: ...controlled markers 31 3 4 2 Idle length An idle character is a character where the start bit all data bits and stop bits are in the mark postion The CTRL ILT register can be configured to start detect...

Page 848: ...f transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits which are sent to the LPUART The IrDA physical layer specification defines a half duplex infr...

Page 849: ...can optionally generate hardware interrupt requests Transmit data register empty LPUART_STAT TDRE indicates when there is room in the transmit data buffer to write another transmit character to LPUART...

Page 850: ...T RDRF These flags are not set in overrun cases If LPUART_STAT RDRF was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer the overrun LPUA...

Page 851: ...ce within the system memory map that is accessible only to the processor core The MMDVSQ module supports execution of the integer divide operations defined in the Armv7 M instruction set architecture...

Page 852: ...tra low end microcontrollers is shown in Figure 32 1 The MMDVSQ module s location as a memory mapped co processor is highlighted AXBS CM0 Core Platform FMC LD ST Dbg Cortex M0 Core AHB Bus AGU RAM Arr...

Page 853: ...its programming model All functionality associated with the MMDVSQ module resides in the core platform s clock domain this includes its connections with the crossbar slave port To minimize power dissi...

Page 854: ...any instant in time the MMDVSQ can perform either a divide or square root calculation The basic integer operations supported by the MMDVSQ are For divide MMDVSQ_RES quotient MMDVSQ_DEND MMDVSQ_DSOR MM...

Page 855: ...ng a calculation causes the access to be stalled using wait states until the calculation completes Address F000_4000h base 0h offset F000_4000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1...

Page 856: ...00_4004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DIVISOR W Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Notes x Undefined a...

Page 857: ...g wait states until the calculation completes Address F000_4000h base 8h offset F000_4008h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R BUSY DIV SQRT 0 W Reset 0 x x 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 858: ...ved and always has the value 0 5 DFS Disable Fast Start The MMDVSQ supports 2 mechanisms for initiating a divide operation The default mechanism is a fast start where a write to the DSOR register begi...

Page 859: ...11 perform an unsigned divide returning the remainder 0 Return the quotient in the RES for the divide calculation 1 Return the remainder in the RES for the divide calculation 1 USGN Unsigned calculati...

Page 860: ...otes x Undefined at reset MMDVSQx_RES field descriptions Field Description RESULT Result This is the output result for a divide or square root calculation 32 3 5 Radicand Register MMDVSQx_RCND The wri...

Page 861: ...is the same as the sign of the dividend The quotient is negated if the signs of the dividend and divisor are different The hardware implementation processes two bits per machine cycle and includes ear...

Page 862: ...Processing two bits of the radicand per cycle the result register finishes with the integer portion of the square root calculation The module includes early termination logic so that the execution ti...

Page 863: ...grammer The Q notation is written as Qm n where Q designates that the number is in the Q format notation the Texas Instruments representation for signed fixed point numbers the Q being reminiscent of...

Page 864: ...0_0003 uQ32 0 0x0000_0001 uQ16 00 1 0 43 581 0x0003_243F uQ16 16 0x0000_01C5 uQ08 08 1 76953125 0 165 0x0324_3F6A uQ08 24 0x0000_1C5B uQ04 12 1 772216769 0 013 0x3243_F6A8 uQ04 28 0x0000_716F uQ02 14...

Page 865: ...0_0000_0000_00 01 1x 2 0000_0000_0000_0000__0000_0000_0000_0000 1 Table 32 5 Square Root Execution Times RCND 31 0 Execution Time with CSR BUSY 1 cycles 01 1x xx_xxxx_xxxx_xxxx__xxxx_xxxx_xxxx_xxxx 17...

Page 866: ...oaded into the register Note a stalled bus cycle cannot be interrupted so if system interrupt latency is a concern the processor should execute a simple wait loop for example polling CSR BUSY before r...

Page 867: ...the following sequence can be used for the context reload 1 Write 0x0000_0020 to the CSR to disable the fast start mechanism 2 Reload DEND DSOR CSR and RES registers from the saved state Since the ori...

Page 868: ...Integer square root K32 L2A Reference Manual Rev 2 01 2020 868 NXP Semiconductors...

Page 869: ...tion Crossbar master arbitration policy selection Flash controller speculation buffer and cache configurations 33 2 Memory map register descriptions The memory map and register descriptions found here...

Page 870: ...nce of bus slave connections to the device s crossbar switch Address F000_3008h base 8h offset F000_3010h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 ASC Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1...

Page 871: ...g connection to the AXBS master input port 0 A bus master connection to AXBS input port n is absent 1 A bus master connection to AXBS input port n is present 33 2 3 Platform Control Register MCMx_PLAC...

Page 872: ...and on for data 0 1 1 Cache is off for both instruction and data 1 X X Cache is off Address F000_3008h base Ch offset F000_3014h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 ESFC W Reset 0...

Page 873: ...r when flash is busy 15 DFCS Disable Flash Controller Speculation Disables flash controller speculation 0 Enable flash controller speculation 1 Disable flash controller speculation 14 EFDS Enable Flas...

Page 874: ...s reserved and always has the value 0 33 2 4 Compute Operation Control Register MCMx_CPO This register controls the Compute Operation Address F000_3008h base 40h offset F000_3048h Bit 31 30 29 28 27 2...

Page 875: ...t has not completed 0 CPOREQ Compute Operation Request This bit is auto cleared by vector fetching if CPOWOI 1 0 Request is cleared 1 Request Compute Operation 33 3 Functional description This section...

Page 876: ...any of the following is true ISCR ETBI is set when The ETB counter is enabled ETBCC CNTEN 1 The ETB count expires The response to counter expiration is a normal interrupt ETBCC RSPT 01 Functional desc...

Page 877: ...to more appropriate values More specifically the core accesses configuration information from a common set of peripheral addresses and the chip configuration logic properly evaluates configuration inf...

Page 878: ...his section are read as zero RAZ Reads from any other bus master return all zeroes Attempted user mode or write accesses are terminated with an error MSCM memory map Absolute address hex Register name...

Page 879: ...Register MSCM_OCMDR2 32 R W See section 34 4 12 887 34 4 2 Processor X Type Register MSCM_CPxTYPE The register provides a CPU specific response indicating the personality of the core making the access...

Page 880: ...gical processor number is always 0 Address 4000_1000h base 4h offset 4000_1004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9...

Page 881: ...r Address 4000_1000h base 8h offset 4000_1008h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PPN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 882: ...MSCM_CPxCOUNT field descriptions Field Description 31 2 Reserved This field is reserved This read only field is reserved and always has the value 0 PCNT Processor Count This read only field defines t...

Page 883: ...Level 1 Data Cache Size This read only field provides an encoded value of the Data Cache size The capacity of the memory is expressed as Size bytes 2 8 SZ where SZ is non zero a SZ 0 indicates the me...

Page 884: ...sor number of the core making the access The logical processor number is always 0 Address 4000_1000h base 24h offset 4000_1024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0...

Page 885: ...or Address 4000_1000h base 28h offset 4000_1028h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PPN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 886: ...d Description 31 2 Reserved This field is reserved This read only field is reserved and always has the value 0 PCNT Processor Count This read only field defines the processor count for the chip config...

Page 887: ...is read only field provides the number of cache ways for the Data Cache 34 4 12 On Chip Memory Descriptor Register MSCM_OCMDRn This section of the programming model is an array of 32 bit generic on ch...

Page 888: ...d to 2d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R V Reserved Reserved OCMSZH OCMSZ Reserved OCMW RO W Reset x 1 x x x x x x x x x x x x x x MSCM Memory Map Register Definition K32 L2A Refe...

Page 889: ...he on chip memory 0 OCMEMn is not present 1 OCMEMn is present 30 Reserved This field is reserved This Reserved field always has the value of 1 29 Reserved This field is reserved 28 OCMSZH OCMEM Size H...

Page 890: ...OCMEMn 64 bits wide 100 111 Reserved 16 RO Read Only This register bit provides a mechanism to lock the configuration state defined by OCMDRn 11 0 Once asserted attempted writes to the OCMDRn 11 0 re...

Page 891: ...e system RAM controller manages requests from two sources AMBA AHB reads and writes from the system bus program trace packet writes from the processor As part of the MTB functionality there is a DWT D...

Page 892: ...on trace port from the processor core The private MTB port signals the instruction address information needed for the 64 bit program trace packets written into the system RAM The PRAM controller outpu...

Page 893: ...on The second higher addressed word contains the destination of the branch the address it branched to The value stored only records bits 31 1 of the branch address The least significant bit of the val...

Page 894: ...responds to approximately 1600 processor cycles per KB This metric is obviously very sensitive to the runtime characteristics of the user code The MTB_DWT function not shown in the core platform block...

Page 895: ...the appropriate crossbar slave port plus the private execution trace bus from the processor core The signals in the private execution trace bus are detailed in the following table taken from the Arm...

Page 896: ...s locations Attempting to access these locations can result in UNPREDICTABLE behavior The behavior of the MTB is UNPREDICTABLE if the registers with UNKNOWN reset values are not programmed prior to en...

Page 897: ...RIPHID4 32 R See section 35 3 1 14 908 F000_0FD4 Peripheral ID Register MTB0_PERIPHID5 32 R See section 35 3 1 14 908 F000_0FD8 Peripheral ID Register MTB0_PERIPHID6 32 R See section 35 3 1 14 908 F00...

Page 898: ...ss 0x2000_0000 In this configuration the MTB_POSITION register is initialized to 0x2000_0000 0x0000_7FF8 0x0000_00000 Following these two suggested placements provides a full featured circular memory...

Page 899: ...Z WI Therefore the active bits in this field are POSITION 16 3 POSITION POINTER 13 0 2 WRAP WRAP This field is set to 1 automatically when the POINTER value wraps as determined by the MTB_MASTER MASK...

Page 900: ...set to 0 because MTB_FLOW WATERMARK is set then it is not automatically set to 1 if TSTARTEN is 1 and the TSTART input is HIGH In this case tracing can only be restarted if MTB_FLOW WATERMARK or MTB_P...

Page 901: ...set to 0 and the MTB_POSITION 14 MASK 3 MTB_POSITION POINTER 11 MASK 1 bits remain unchanged This field causes the trace packet information to be stored in a circular buffer of size 2 MASK 4 bytes tha...

Page 902: ...he WATERMARK field value actions defined by the AUTOHALT and AUTOSTOP bits are performed 2 Reserved This field is reserved This read only field is reserved and always has the value 0 1 AUTOHALT AUTOHA...

Page 903: ...iption BASEADDR BASEADDR This value is defined hardwired 0x1FFF_8000 Core 0 35 3 1 5 Integration Mode Control Register MTBx_MODECTRL This register enables the device to switch from a functional mode o...

Page 904: ...x0000_0000 35 3 1 7 Claim TAG Clear Register MTBx_TAGCLEAR The read write Claim Tag Clear Register is used to read the claim status on debug resources A read indicates the claim tag status Writing 1 t...

Page 905: ...ess Register It is hardwired to specific values used during the auto discovery process by an external debug agent Address F000_0000h base FB4h offset F000_0FB4h Bit 31 30 29 28 27 26 25 24 23 22 21 20...

Page 906: ...read only field is reserved and always has the value 0 3 Reserved BIT3 This read only field is reserved and always has the value 1 2 BIT2 BIT2 Connected to NIDEN or DBGEN signal 1 Reserved BIT1 This...

Page 907: ...0 MTBx_DEVICECFG field descriptions Field Description DEVICECFG DEVICECFG Hardwired to 0x0000_0000 35 3 1 13 Device Type Identifier Register MTBx_DEVICETYPID This register indicates the device type ID...

Page 908: ...Component ID Register MTBx_COMPIDn These registers indicate the component IDs They are hardwired to specific values used during the auto discovery process by an external debug agent Address F000_0000h...

Page 909: ...egister MTB0_DWT_DEVICETYPID 32 R 0000_0004h 35 3 2 8 917 F000_1FD0 Peripheral ID Register MTB0_DWT_PERIPHID4 32 R See section 35 3 2 9 918 F000_1FD4 Peripheral ID Register MTB0_DWT_PERIPHID5 32 R See...

Page 910: ...BDWT_CTRL 25 NOCYCCNT 1 cycle counter is not supported MTBDWT_CTRL 24 NOPRFCNT 1 profiling counters are not supported MTBDWT_CTRL 22 CYCEBTENA 0 no POSTCNT underflow packets generated MTBDWT_CTRL 21 F...

Page 911: ...gnore mask applied to the reference address for address range matching by comparator n Note the format of this mask field is different than the MTB_MASTER MASK Address F000_1000h base 24h offset 16d i...

Page 912: ...lue comparator then MTBDWT_MASK0 should be programmed to zero 35 3 2 4 MTB_DWT Comparator Function Register 0 MTBx0_DWT_FCT0 The MTBDWT_FCTn registers control the operation of comparator n Address F00...

Page 913: ...size of the required data comparison 00 Byte 01 Halfword 10 Word 11 Reserved Any attempts to use this value results in UNPREDICTABLE behavior 9 Reserved This field is reserved This read only field is...

Page 914: ...11 10 8 Address F000_1000h base 38h offset F000_1038h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 MATCHED 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 915: ...etch 0101 Data operand read 0110 Data operand write 0111 Data operand read write others Reserved Any attempts to use this value results in UNPREDICTABLE behavior 35 3 2 6 MTB_DWT Trace Buffer Control...

Page 916: ...e assertion of MTBDWT_FCT1 MATCHED 1 Trigger TSTART based on the assertion of MTBDWT_FCT1 MATCHED 0 ACOMP0 Action based on Comparator 0 match When the MTBDWT_FCT0 MATCHED is set it indicates MTBDWT_CO...

Page 917: ...ion DEVICECFG DEVICECFG Hardwired to 0x0000_0000 35 3 2 8 Device Type Identifier Register MTBx0_DWT_DEVICETYPID This register indicates the device type ID It is hardwired to specific values used durin...

Page 918: ...0 Component ID Register MTBx0_DWT_COMPIDn These registers indicate the component IDs They are hardwired to specific values used during the auto discovery process by an external debug agent Address F00...

Page 919: ...CPUID Debug control Data watchpoint unit CoreSight ID Watchpoint control Breakpoint unit CoreSight ID Breakpoint control Optional component Figure 35 3 CoreSight discovery process MTB_ROM memory map A...

Page 920: ..._2FF0 Component ID Register MTB0_ROM_COMPID0 32 R See section 35 3 3 5 922 F000_2FF4 Component ID Register MTB0_ROM_COMPID1 32 R See section 35 3 3 5 922 F000_2FF8 Component ID Register MTB0_ROM_COMPI...

Page 921: ...3 2 1 0 R MARK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTBx0_ROM_TABLEMARK field descriptions Field Description MARK MARK Hardwired to 0x0000_0000 35 3 3 3 System Acces...

Page 922: ...ID Peripheral ID1 is hardwired to 0x0000_00E0 ID2 to 0x0000_0008 and all the others to 0x0000_0000 35 3 3 5 Component ID Register MTBx0_ROM_COMPIDn These registers indicate the component IDs They are...

Page 923: ...the system to control and acknowledge the Stop Doze and Debug signals 36 1 1 Features The PCC module enables software to configure the following clocking options for each peripheral Clock gating Clock...

Page 924: ...cted if PCS 000 Clock Gate Control Clock Gate PCC Register values Test Control Signals Peripheral Interface Clock This clock is used by PCC Control and Config Registers Slow System Clock or Platform C...

Page 925: ...PCC_LPSPI2 32 RW 80000000h 4007A108h PCC LPI2C2 PCC_LPI2C2 32 RW 80000000h 4007A118h PCC LPUART2 PCC_LPUART2 32 RW 80000000h 4007A138h PCC EMVSIM0 PCC_EMVSIM0 32 RW 80000000h 4007A154h PCC USB0FS PCC_...

Page 926: ...present on this device 0 Peripheral is not present 1 Peripheral is present 30 CGC This read write bit enables the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE This read only bit...

Page 927: ...d Reserved W Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 2 1 3 3 Fields Field Function 31...

Page 928: ...is reserved and always has the value 0 2 0 This read only bit field is reserved and always has the value 0 36 2 1 4 PCC DMAMUX0 PCC_DMAMUX0 36 2 1 4 1 Address Register Offset PCC_DMAMUX0 4007A084h PC...

Page 929: ...is being used 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This read only bit field is reserved and...

Page 930: ...s the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE This read only bit indicates the peripheral is being used 0 Peripheral is not being used 1 Peripheral is being used 28 27 This...

Page 931: ...he clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE This read only bit indicates the peripheral is being used 0 Peripheral is not being used 1 Peripheral is being used 28 27 This rea...

Page 932: ...d and always has the value 0 36 2 1 7 PCC LPIT0 PCC_LPIT0 36 2 1 7 1 Address Register Offset PCC_LPIT0 4007A0C0h PCC Register 36 2 1 7 2 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R...

Page 933: ...selections This field can only be written when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000 Clock is off or test clock is enabled 001 OSCCLK System Oscil...

Page 934: ...ead write bit enables the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE This read only bit indicates the peripheral is being used 0 Peripheral is not being used 1 Peripheral is be...

Page 935: ...resent on this device 0 Peripheral is not present 1 Peripheral is present 30 CGC This read write bit enables the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE This read only bit i...

Page 936: ...eserved PCS Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 2 1 10 3 Fields Field F...

Page 937: ...field is locked 000 Clock is off or test clock is enabled 001 OSCCLK System Oscillator Bus Clock 010 SCGIRCLK Slow IRC Clock 011 SCGFIRCLK Fast IRC Clock 100 Reserved 101 Reserved 110 SCGPCLK System...

Page 938: ...t being used 1 Peripheral is being used 28 27 This read only bit field is reserved and always has the value 0 26 24 PCS This read write bit field is used for peripherals that support various clock sel...

Page 939: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 2 1 12 3 Fields Field Function 31 PR This bit shows whether the peripheral is present on this d...

Page 940: ...test clock is enabled 001 OSCCLK System Oscillator Bus Clock 010 SCGIRCLK Slow IRC Clock 011 SCGFIRCLK Fast IRC Clock 100 Reserved 101 Reserved 110 SCGPCLK System PLL clock 111 Reserved 23 4 This read...

Page 941: ...being used 1 Peripheral is being used 28 27 This read only bit field is reserved and always has the value 0 26 24 PCS This read write bit field is used for peripherals that support various clock selec...

Page 942: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved FRAC PCD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 2 1 14 3 Fields Field Function 31 PR This bit shows whether the peripheral is present on this devic...

Page 943: ...his read write bit field sets the fraction multiply value for the fractional clock divider used as a clock source Divider output clock Divider input clock x FRAC 1 DIV 1 This field can only be written...

Page 944: ...t present 1 Peripheral is present 30 CGC This read write bit enables the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE This read only bit indicates the peripheral is being used 0...

Page 945: ...5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 2 1 16 3 Fields Field Function 31 PR This bit shows whether the peripheral is present on this device 0 Peripheral...

Page 946: ...read only bit field is reserved and always has the value 0 36 2 1 17 PCC PORTC PCC_PORTC 36 2 1 17 1 Address Register Offset PCC_PORTC 4007A170h PCC Register 36 2 1 17 2 Diagram Bits 31 30 29 28 27 2...

Page 947: ...al is being used 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This read only bit field is reserved a...

Page 948: ...s the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE This read only bit indicates the peripheral is being used 0 Peripheral is not being used 1 Peripheral is being used 28 27 This...

Page 949: ...resent 1 Peripheral is present 30 CGC This read write bit enables the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE This read only bit indicates the peripheral is being used 0 Per...

Page 950: ...6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 2 1 20 3 Fields Field Function 31 PR This bit shows whether the peripheral is present on this device 0 Peripheral...

Page 951: ...is read only bit field is reserved and always has the value 0 36 2 1 21 PCC ADC0 PCC_ADC0 36 2 1 21 1 Address Register Offset PCC_ADC0 4007A198h PCC Register 36 2 1 21 2 Diagram Bits 31 30 29 28 27 26...

Page 952: ...clock selections This field can only be written when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000 Clock is off or test clock is enabled 001 OSCCLK System...

Page 953: ...ad write bit enables the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE This read only bit indicates the peripheral is being used 0 Peripheral is not being used 1 Peripheral is bei...

Page 954: ...l is present on this device 0 Peripheral is not present 1 Peripheral is present 30 CGC This read write bit enables the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE This read only...

Page 955: ...Reserved Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 2 1 24 3 Fields Field Func...

Page 956: ...ly bit field is reserved and always has the value 0 2 0 This read only bit field is reserved and always has the value 0 36 2 1 25 PCC CRC PCC_CRC 36 2 1 25 1 Address Register Offset PCC_CRC 4007A1E0h...

Page 957: ...ys has the value 0 2 0 This read only bit field is reserved and always has the value 0 36 2 2 PCC Register Descriptions These register may not be applicable to all instances of PCC For more details on...

Page 958: ...00000h 36 2 2 1 PCC Register Descriptions 36 2 2 2 PCC TRNG PCC_TRNG 36 2 2 2 1 Address Register Offset PCC_TRNG 400FA094h 36 2 2 2 2 Function PCC Register 36 2 2 2 3 Diagram Bits 31 30 29 28 27 26 25...

Page 959: ...used 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This read only bit field is reserved and always h...

Page 960: ...28 27 This read only bit field is reserved and always has the value 0 26 24 PCS This read write bit field is used for peripherals that support various clock selections At SOC integration each periphe...

Page 961: ...served PCS Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 2 2 4 3 Fields Field Fun...

Page 962: ...clock disabled Likewise if the INUSE flag is set this field is locked 000 Clock is off or test clock is enabled 001 OSCCLK System Oscillator Bus Clock 010 SCGIRCLK Slow IRC Clock 011 SCGFIRCLK Fast I...

Page 963: ...he peripheral 0 Clock disabled 1 Clock enabled 29 INUSE This read only bit indicates the peripheral is being used 0 Peripheral is not being used 1 Peripheral is being used 28 27 This read only bit fie...

Page 964: ...nabled 29 INUSE This read only bit indicates the peripheral is being used 0 Peripheral is not being used 1 Peripheral is being used 28 27 This read only bit field is reserved and always has the value...

Page 965: ...is reserved and always has the value 0 36 2 2 7 PCC LPSPI1 PCC_LPSPI1 36 2 2 7 1 Address Register Offset PCC_LPSPI1 400FA0F4h PCC Register 36 2 2 7 2 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 966: ...slow clock source choices or the fast clock source choices This field can only be written when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000 Clock is off...

Page 967: ...is not being used 1 Peripheral is being used 28 27 This read only bit field is reserved and always has the value 0 26 24 PCS This read write bit field is used for peripherals that support various clo...

Page 968: ...gister 36 2 2 9 2 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PR CGC INUS E Reserved PCS Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 969: ...ield can only be written when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000 Clock is off or test clock is enabled 001 OSCCLK System Oscillator Bus Clock 01...

Page 970: ...d 28 27 This read only bit field is reserved and always has the value 0 26 24 PCS This read write bit field is used for peripherals that support various clock selections At SOC integration each periph...

Page 971: ...E Reserved PCS Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 2 2 11 3 Fields Fie...

Page 972: ...lock disabled Likewise if the INUSE flag is set this field is locked 000 Clock is off or test clock is enabled 001 OSCCLK System Oscillator Bus Clock 010 SCGIRCLK Slow IRC Clock 011 SCGFIRCLK Fast IRC...

Page 973: ...8 27 This read only bit field is reserved and always has the value 0 26 24 PCS This read write bit field is used for peripherals that support various clock selections At SOC integration each periphera...

Page 974: ...eserved Reserved Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 2 2 13 3 Fields Fi...

Page 975: ...unctional description The Peripheral Clock Control PCC module provides clock gating and clock source selection to each peripheral Each peripheral has it s own unique PCCn register that provide clock g...

Page 976: ...Functional description K32 L2A Reference Manual Rev 2 01 2020 976 NXP Semiconductors...

Page 977: ...of included PMC features can be found here Internal voltage regulator Active POR providing brown out detect Low voltage detect LVD on VDD supporting two low voltage trip points with four warning leve...

Page 978: ...only if the internal supply has returned above the trip point otherwise LVDSC2 LVWF remains set 37 3 1 LVD reset operation By setting LVDSC1 LVDRE the LVD generates a reset upon detection of a low vo...

Page 979: ...ct system The High Voltage Detect Flag in the High Voltage Status and Control 1 Register HVDSC1 HVDF operates in a level sensitive manner HVDSC1 HVDF is set when the supply voltage rises above the sel...

Page 980: ...ate When in VLLS modes the I O states are held on a wake up event with the exception of wake up by reset event until the wake up has been acknowledged via a write to REGSC ACKISO In the case of VLLS e...

Page 981: ...00_0001h 37 6 6 988 37 6 1 Version ID register PMC_VERID Address 4007_D000h base 0h offset 4007_D000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MAJOR...

Page 982: ...the value 0 1 HVDE HVD Enabled If set indicates support for High Voltage Detect is enabled 0 VLPOE VLPO Enable If set indicates support for VLPO bit is enabled in the PMC_REGSC register 37 6 3 Low Vol...

Page 983: ...ts are reset on Chip Reset Not VLLS For more information about these reset types refer to the Reset section details Address 4007_D000h base 8h offset 4007_D008h Bit 31 30 29 28 27 26 25 24 23 22 21 20...

Page 984: ...al writes are ignored 0 LVDF does not generate hardware resets 1 Force an MCU reset when LVDF 1 3 2 Reserved This field is reserved This read only field is reserved and always has the value 0 LVDV Low...

Page 985: ...8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 LVWF Low Voltage Warning Flag This read only status field indicates a low voltage warning event LVWF is...

Page 986: ...ed VLVW VLVW2 10 Mid 2 trip point selected VLVW VLVW3 11 High trip point selected VLVW VLVW4 37 6 5 Regulator Status And Control register PMC_REGSC The PMC contains an internal voltage regulator The v...

Page 987: ...ation VLPx LLS and VLLSx When on chip peripherals require the bandgap voltage reference in low power modes of operation set BGEN to continue to enable the bandgap operation NOTE When the bandgap volta...

Page 988: ...his register contains status and control bits to support the high voltage detect function This register should be written during the reset initialization program to set the desired controls even if th...

Page 989: ...s read only status field indicates a high voltage detect event 0 High voltage event not detected 1 High voltage event detected 6 HVDACK High Voltage Detect Acknowledge This write only field is used to...

Page 990: ...hardware resets 1 Force an MCU reset when HVDF 1 3 1 Reserved This field is reserved This read only field is reserved and always has the value 0 0 HVDV High Voltage Detect Voltage Select Selects the...

Page 991: ...sabled Disabled Disabled Slew rate enable control Yes Yes Yes Yes Yes Slew rate enable after reset PTA3 Disabled Others Enabled Enabled Enabled Enabled Enabled Passive filter enable control PTA4 and P...

Page 992: ...ere is one instance of the PORT module for each port Not all pins within each port are implemented on a specific device 38 2 2 Features The PORT module has the following features Pin interrupt Interru...

Page 993: ...ield supporting analog or pin disabled GPIO and up to six chip specific digital functions Pad configuration fields are functional in all digital pin muxing modes 38 2 3 Modes of operation 38 2 3 1 Run...

Page 994: ...38 3 PORT interface detailed signal description Signal I O Description PORTx 31 0 I O External interrupt State meaning Asserted pin is logic 1 Negated pin is logic 0 Timing Assertion may occur at any...

Page 995: ...egister n PORTA_PCR16 32 R W See section 38 5 1 1001 4005_A044 Pin Control Register n PORTA_PCR17 32 R W See section 38 5 1 1001 4005_A048 Pin Control Register n PORTA_PCR18 32 R W See section 38 5 1...

Page 996: ...1 1001 4005_B028 Pin Control Register n PORTB_PCR10 32 R W See section 38 5 1 1001 4005_B02C Pin Control Register n PORTB_PCR11 32 R W See section 38 5 1 1001 4005_B030 Pin Control Register n PORTB_P...

Page 997: ...00C Pin Control Register n PORTC_PCR3 32 R W See section 38 5 1 1001 4005_C010 Pin Control Register n PORTC_PCR4 32 R W See section 38 5 1 1001 4005_C014 Pin Control Register n PORTC_PCR5 32 R W See s...

Page 998: ...PORTC_GICHR 32 W always reads 0 0000_0000h 38 5 5 1005 4005_C0A0 Interrupt Status Flag Register PORTC_ISFR 32 w1c 0000_0000h 38 5 6 1006 4005_C0C0 Digital Filter Enable Register PORTC_DFER 32 R W 000...

Page 999: ...W See section 38 5 1 1001 4005_D074 Pin Control Register n PORTD_PCR29 32 R W See section 38 5 1 1001 4005_D078 Pin Control Register n PORTD_PCR30 32 R W See section 38 5 1 1001 4005_D07C Pin Control...

Page 1000: ...20 32 R W See section 38 5 1 1001 4005_E054 Pin Control Register n PORTE_PCR21 32 R W See section 38 5 1 1001 4005_E058 Pin Control Register n PORTE_PCR22 32 R W See section 38 5 1 1001 4005_E05C Pin...

Page 1001: ...0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R LK 0 MUX 0 DSE ODE PFE 0 SRE PE PS W Reset 0 0 0 0 0 0 0 0 Notes MUX field Varies by port See Signal Multiplexing and Signal Descriptions...

Page 1002: ...lling edge 0111 Flag sets on either edge 1000 ISF flag and Interrupt when logic 0 1001 ISF flag and Interrupt on rising edge 1010 ISF flag and Interrupt on falling edge 1011 ISF flag and Interrupt on...

Page 1003: ...des 0 Passive input filter is disabled on the corresponding pin 1 Passive input filter is enabled on the corresponding pin if the pin is configured as a digital input Refer to the device data sheet fo...

Page 1004: ...egisters 15 through 0 bits 15 0 update with the value in GPWD If a selected Pin Control Register is locked then the write to that register is ignored 0 Corresponding Pin Control Register is not update...

Page 1005: ...Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_GICLR field descriptions Field Description 31 16 GIWD Global Interrupt Write Data Write value that is written to all Pin Co...

Page 1006: ...ISF W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_ISFR field descriptions Field Description ISF Interrupt Status Flag Each bit in the field indicates the detection...

Page 1007: ...al input 38 5 8 Digital Filter Clock Register PORTx_DFCR This register is read only for ports that do not support a digital filter The digital filter configuration is valid in all digital pin muxing m...

Page 1008: ...ng will pass through the digital filter and glitches that are equal to or less than this register setting are filtered Changing the filter length must be done only after all filters are disabled 38 6...

Page 1009: ...when its input buffer is enabled then this can cause an increase in power consumption and must be avoided A pin can be floating due to an input pin that is not connected or an output pin that has tri...

Page 1010: ...for software polling Active high level peripheral trigger status flag disabled Active low level peripheral trigger status flag disabled Active high level sensitive interrupt Active low level sensitive...

Page 1011: ...k This selection must be changed only when all digital filters for that port are disabled If the digital filters for a port are configured to use the bus clock then the digital filters are bypassed fo...

Page 1012: ...Functional description K32 L2A Reference Manual Rev 2 01 2020 1012 NXP Semiconductors...

Page 1013: ...isters provide reset status information and reset filter control NOTE The RCM registers can be written only in supervisor mode Write accesses in user mode are blocked and will result in a bus error RC...

Page 1014: ...07_F000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MAJOR MINOR FEATURE W Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 RCM_VER...

Page 1015: ...EMDM_AP ESW ELOCKUP EJTAG EPOR EPIN EWDOG ECMU_LOC ELOL ELOC ELVD EWAKEUP W Reset 0 0 1 0 1 1 1 0 1 1 1 0 1 1 1 1 RCM_PARAM field descriptions Field Description 31 17 Reserved This field is reserved T...

Page 1016: ...This static bit states whether or not the feature is available on the device 0 The feature is not available 1 The feature is available 10 ESW Existence of SRS SW status indication feature This static...

Page 1017: ...le 1 The feature is available 2 ELOC Existence of SRS LOC status indication feature This static bit states whether or not the feature is available on the device 0 The feature is not available 1 The fe...

Page 1018: ...0 SACKERR 0 MDM_AP SW LOCKUP 0 POR PIN WDOG 0 LOL LOC LVD WAKEUP W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 RCM_SRS field descriptions Field Description 31 17 Reserved This field is reserved This read o...

Page 1019: ...by software setting of SYSRESETREQ bit 1 Reset caused by software setting of SYSRESETREQ bit 9 LOCKUP Core Lockup Indicates a reset has been caused by the Arm core indication of a LOCKUP event 0 Rese...

Page 1020: ...LVD Low Voltage Detect Reset or High Voltage Detect Reset If PMC_LVDSC1 LVDRE is set and the supply drops below the LVD trip voltage an LVD reset occurs If PMC_HVDSC1 HVDRE is set and the supply rise...

Page 1021: ...1 cycles inclusive may be filtered Transition lengths greater than RSTFLTSEL 1 cycles are not filtered 7 3 Reserved This field is reserved This read only field is reserved and always has the value 0...

Page 1022: ...ROM Configuration Indicates the boot source the boot source remains set until the next System Reset or software can write logic one to clear the corresponding mode bit While either bit is set the NMI...

Page 1023: ...0 0 RCM_FM field descriptions Field Description 31 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 1 FORCEROM Force ROM Boot When either bit is set will...

Page 1024: ...L SLOC SLVD SWAKEUP W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 RCM_SSRS field descriptions Field Description 31 17 Reserved This field is reserved This read on...

Page 1025: ...ng of SYSRESETREQ bit 9 SLOCKUP Sticky Core Lockup Indicates a reset has been caused by the Arm core indication of a LOCKUP event 0 Reset not caused by core LOCKUP event 1 Reset caused by core LOCKUP...

Page 1026: ...below the LVD trip voltage an LVD reset occurs This field is also set by POR 0 Reset not caused by LVD trip or POR 1 Reset caused by LVD trip or POR 0 SWAKEUP Sticky VLLS Wakeup Reset Indicates a rese...

Page 1027: ...Reserved This field is reserved This read only field is reserved and always has the value 0 13 SACKERR Stop Acknowledge Error Interrupt 0 Interrupt disabled 1 Interrupt enabled 12 Reserved This field...

Page 1028: ...sabled 1 Interrupt enabled 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 LOL Loss of Lock Interrupt 0 Interrupt disabled 1 Interrupt enabled 2 LOC Los...

Page 1029: ...function The GPIO input data register displays the logic value on each pin when the pin is configured for any digital function provided the corresponding Port Control and Interrupt module for that pin...

Page 1030: ...purpose input output I O PORTD31 PORTD0 General purpose input output I O PORTE31 PORTE0 General purpose input output I O NOTE Not all pins within each port are implemented on each device See the chap...

Page 1031: ...ster name Width in bits Access Reset value Section page 4000_F000 Port Data Output Register GPIOA_PDOR 32 R W 0000_0000h 40 2 1 1033 4000_F004 Port Set Output Register GPIOA_PSOR 32 W always reads 0 0...

Page 1032: ...000_0000h 40 2 6 1035 4000_F0C0 Port Data Output Register GPIOD_PDOR 32 R W 0000_0000h 40 2 1 1033 4000_F0C4 Port Set Output Register GPIOD_PSOR 32 W always reads 0 0000_0000h 40 2 2 1033 4000_F0C8 Po...

Page 1033: ...ed value when read 0 Logic level 0 is driven on pin provided pin is configured for general purpose output 1 Logic level 1 is driven on pin provided pin is configured for general purpose output 40 2 2...

Page 1034: ...bit in PDORn does not change 1 Corresponding bit in PDORn is cleared to logic 0 40 2 4 Port Toggle Output Register GPIOx_PTOR Address Base address Ch offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 1035: ...Interrupt module is disabled then the corresponding bit in PDIR does not update 0 Pin logic level is logic 0 or is not configured for use by digital function 1 Pin logic level is logic 1 40 2 6 Port D...

Page 1036: ...ster FGPIOA_PDOR 32 R W 0000_0000h 40 3 1 1036 F800_0004 Port Set Output Register FGPIOA_PSOR 32 W always reads 0 0000_0000h 40 3 2 1037 F800_0008 Port Clear Output Register FGPIOA_PCOR 32 W always re...

Page 1037: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FGPIOx_PSOR field descriptions Field Description PTSO Port Set Output Writing to this register will update the contents of the corresponding bit in the PDOR as follows 0...

Page 1038: ...DOR as follows 0 Corresponding bit in PDORn does not change 1 Corresponding bit in PDORn is set to the inverse of its existing logic state 40 3 5 Port Data Input Register FGPIOx_PDIR Address F800_0000...

Page 1039: ...put registers provided the pin is configured for a digital function and the corresponding Port Control and Interrupt module is enabled 40 4 2 General purpose output The logic state of each pin can be...

Page 1040: ...the IOPORT interface on the Cortex M0 from address 0xF800_0000 Accesses via the IOPORT interface occur in parallel with any instruction fetches and will therefore complete in a single cycle If the DMA...

Page 1041: ...that can correct errors between 0 12 ppm and 3906 ppm Option to increment prescaler using the LPO prescaler increments by 32 every clock edge Register write protection Lock register requires POR or so...

Page 1042: ...Writing to a register protected by the lock register does not generate a bus error but the write will not complete RTC memory map Absolute address hex Register name Width in bits Access Reset value Se...

Page 1043: ...ause TSR will read as zero when SR TIF or SR TOF are set indicating the time is invalid 41 2 2 RTC Time Prescaler Register RTC_TPR Address 4003_8000h base 4h offset 4003_8004h Bit 31 30 29 28 27 26 25...

Page 1044: ...ents of the CIR If the CIC does not equal zero then it is decremented once a second 23 16 TCV Time Compensation Value Current value used by the compensation logic for the present second interval Updat...

Page 1045: ...egister RTC_CR Address 4003_8000h base 10h offset 4003_8010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 CPE 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 1046: ...Oscillator Enable 0 32 768 kHz oscillator is disabled 1 32 768 kHz oscillator is enabled After setting this bit wait the oscillator startup time before enabling the time counter to allow the 32 768 k...

Page 1047: ...an be written when locked under limited conditions 2 SUP Supervisor Access 0 Non supervisor mode write accesses are not supported and generate a bus error 1 Non supervisor mode write accesses are supp...

Page 1048: ...is set when the time counter is enabled and overflows The TSR and TPR do not increment and read as zero when this bit is set This bit is cleared by writing the TSR register when the time counter is d...

Page 1049: ...ared this bit can only be set by POR 0 Control Register is locked and writes are ignored 1 Control Register is not locked and writes complete as normal 3 TCL Time Compensation Lock After being cleared...

Page 1050: ...pin is enabled then the wakeup pin will assert 6 5 Reserved This field is reserved 4 TSIE Time Seconds Interrupt Enable The seconds interrupt is an edge sensitive interrupt with a dedicated interrupt...

Page 1051: ...bling the cystal oscillator wait the oscillator startup time before setting SR TCE or using the oscillator clock external to the RTC The crystal oscillator includes tunable capacitors that can be conf...

Page 1052: ...set SR TIF is clear SR TOF is clear and the 32 768 kHz or 1 kHz clock source is present After enabling the oscillator wait the oscillator startup time before setting SR TCE to allow time for the osci...

Page 1053: ...seconds register increments and provided the previous compensation interval has expired When the compensation interval is set to other than once a second then the compensation is applied in the first...

Page 1054: ...ed and do not generate a bus error 41 3 7 Interrupt The RTC interrupt is asserted whenever a status flag and the corresponding interrupt enable bit are both set It is always asserted on POR and softwa...

Page 1055: ...elect either the output clock of the SPLL or a SCG reference clock SIRC FIRC and SOSC as the source for the MCU system clocks The SCG also supports operation with crystal oscillators which allows an e...

Page 1056: ...IRC which can be used as clock sources for other on chip peripherals System Crystal Oscillator Can be used as a source for the System PLL Can be selected as the clock source for the MCU system clocks...

Page 1057: ...ator SCG block diagram NOTE To identify the oscillator used in your specific MCU device see the chip configuration chapter 42 2 Memory Map Register Definition This section includes the memory map and...

Page 1058: ...4007_B108 System Oscillator Configuration Register SCG_SOSCCFG 32 R W 0000_0010h 42 2 10 1073 4007_B200 Slow IRC Control Status Register SCG_SIRCCSR 32 R W 0300_0005h 42 2 11 1074 4007_B204 Slow IRC D...

Page 1059: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Notes DIVPRES field The reset value is controlled by which SCG System Dividers are used by Soc CLKPRES field The reset value is controlled by which SCG Clock Sourc...

Page 1060: ...se 10h offset 4007_B010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SCS 0 DIVCORE 0 0 0 DIVSLOW W Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1061: ...e by 15 1111 Divide by 16 15 12 Reserved This field is reserved This read only field is reserved and always has the value 0 11 8 Reserved This field is reserved This read only field is reserved and al...

Page 1062: ...led by user FOPT bits that get uploaded during reset The two valid reset values are div by 1 and div by 2 SCG_RCCR field descriptions Field Description 31 28 Reserved This field is reserved This read...

Page 1063: ...eserved This field is reserved This read only field is reserved and always has the value 0 7 4 Reserved This field is reserved This read only field is reserved and always has the value 0 DIVSLOW Slow...

Page 1064: ...led by user FOPT bits that get uploaded during reset The two option reset values are div by 4 and div by 8 SCG_VCCR field descriptions Field Description 31 28 Reserved This field is reserved This read...

Page 1065: ...d 11 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 4 Reserved This field is reserved This read only field is reserved and always has the value 0 DIVSL...

Page 1066: ...0 0 0 0 0 0 0 0 0 0 0 0 1 SCG_HCCR field descriptions Field Description 31 28 Reserved This field is reserved This read only field is reserved and always has the value 0 27 24 SCS System Clock Source...

Page 1067: ...00 Divide by 1 0001 Divide by 2 0010 Divide by 3 0011 Divide by 4 0100 Divide by 5 0101 Divide by 6 0110 Divide by 7 0111 Divide by 8 1000 Divide by 9 1001 Divide by 10 1010 Divide by 11 1011 Divide b...

Page 1068: ...elects the SCG system clock 0000 SCG SLOW Clock 0001 System OSC SOSC_CLK 0010 Slow IRC SIRC_CLK 0011 Fast IRC FIRC_CLK 0100 Reserved 0101 Reserved 0110 System PLL SPLL_CLK 0111 Reserved 1111 Reserved...

Page 1069: ...R field This flag is reset on Chip POR only SCG_SOSCCSR field descriptions Field Description 31 27 Reserved This field is reserved This read only field is reserved and always has the value 0 26 SOSCER...

Page 1070: ...e clock monitor is always disabled in LLS VLLS modes When the clock monitor is disabled in a low power mode it remains disabled until the clock valid flag is set following exit from the low power mode...

Page 1071: ...Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 SOSCDIV3 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SOSCDIV2 0 SOSCDIV1 W Reset 0 0 0 0 0 0 0 0 0 0...

Page 1072: ...y 32 111 Divide by 64 7 3 Reserved This field is reserved This read only field is reserved and always has the value 0 SOSCDIV1 System OSC Clock Divide 1 Clock divider 1 for System OSC Used to generate...

Page 1073: ...SC2P Oscillator 2 pF Capacitor Load 10 SC4P Oscillator 4 pF Capacitor Load 9 SC8P Oscillator 8 pF Capacitor Load Configure 8 SC16P Oscillator 16 pF Capacitor Load 7 6 Reserved This field is reserved...

Page 1074: ...ystal oscillator of OSC selected In VLLS0 the internal oscillator of OSC is disabled even if SOSCEN 1 and SOSCSTEN 1 Reserved This field is reserved This read only field is reserved and always has the...

Page 1075: ...is reserved and always has the value 0 2 SIRCLPEN Slow IRC Low Power Enable 0 Slow IRC is disabled in VLP modes 1 Slow IRC is enabled in VLP modes 1 SIRCSTEN Slow IRC Stop Enable 0 Slow IRC is disabl...

Page 1076: ...2 Slow IRC Clock Divide 2 Clock divider 2 for Slow IRC Used by modules that need an asynchronous clock source 000 Output disabled 001 Divide by 1 010 Divide by 2 011 Divide by 4 100 Divide by 8 101 Di...

Page 1077: ...W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 RANGE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SCG_SIRCCFG field descriptions Field Description 31 1 Reserved This...

Page 1078: ...descriptions Field Description 31 27 Reserved This field is reserved This read only field is reserved and always has the value 0 26 FIRCERR Fast IRC Clock Error This flag is reset on Chip POR only sof...

Page 1079: ...erved This field is reserved This read only field is reserved and always has the value 0 3 FIRCREGOFF Fast IRC Regulator Enable NOTE When Fast IRC is used FIRCREGOFF must be 0 Fast IRC cannot be opera...

Page 1080: ...ck disabled 001 Divide by 1 010 Divide by 2 011 Divide by 4 100 Divide by 8 101 Divide by 16 110 Divide by 32 111 Divide by 64 15 11 Reserved This field is reserved This read only field is reserved an...

Page 1081: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 RANGE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCG_FIRCCFG field...

Page 1082: ...15 11 Reserved This field is reserved This read only field is reserved and always has the value 0 10 8 TRIMDIV Fast IRC Trim Predivide Divide the System OSC down for Fast IRC trimming 000 Divide by 1...

Page 1083: ...as the value 0 15 14 Reserved This field is reserved This read only field is reserved and always has the value 0 13 8 TRIMCOAR Trim Coarse TRIMCOAR bits are used to coursely trim the Fast IRC Clock to...

Page 1084: ...reset on Chip POR only software can also clear this flag by writing a logic one NOTE The LOL Flag is set when the PLL reference is out of range Dunl in datasheet and is constantly modulated such that...

Page 1085: ...Reserved This field is reserved This read only field is reserved and always has the value 0 17 SPLLCMRE System PLL Clock Monitor Reset Enable 0 Clock Monitor generates interrupt when error detected 1...

Page 1086: ...lock divider 3 for System PLL Used by modules that need an asynchronous clock source 000 Clock disabled 001 Divide by 1 010 Divide by 2 011 Divide by 4 100 Divide by 8 101 Divide by 16 110 Divide by 3...

Page 1087: ...PLL is enabled When the System PLL is enabled writes to this register are ignored and there is no transfer error The below information applies to VCO_CLK The SPLL_CLK VCO_CLK 2 The VCO_CLK SPLL_SOURCE...

Page 1088: ...00101 21 01101 29 10101 37 11101 45 00110 22 01110 30 10110 38 11110 46 00111 23 01111 31 10111 39 11111 47 15 11 Reserved This field is reserved This read only field is reserved and always has the va...

Page 1089: ...2 3 Functional description 42 3 1 SCG Clock Mode Transitions The following figure shows the valid clock mode transitions supported by SCG Fast IRC FIRC boot mode is not supported on this device Chapte...

Page 1090: ...CG Valid Mode Transition Diagram NOTE When a transition between run modes RUN HSRUN VLRUN is required the SCG should complete the switch to the clock mode as defined in the SCG clock control register...

Page 1091: ...his table Slow Internal Reference Clock SIRC Slow Internal Reference Clock SIRC mode is entered when all the following conditions occur RUN MODE 0010 is written to RCCR SCS VLRUN MODE 0010 is written...

Page 1092: ...ed to produce a valid PLL reference clock This divide value is defined by the SCG_SPLLCFG PREDIV bits Information regarding SPLL operation during normal and low power stop modes is found in the Stop r...

Page 1093: ...odes of operation Mode Description SPLLCSR SPLLSTEN 1 SPLLSTEN control bit has no affect in LLS or VLPS Power mode Chapter 42 System Clock Generator SCG K32 L2A Reference Manual Rev 2 01 2020 NXP Semi...

Page 1094: ...Functional description K32 L2A Reference Manual Rev 2 01 2020 1094 NXP Semiconductors...

Page 1095: ...3 2 Memory map and register definition The SIM module contains many bit fields for miscellaneous configuration of the device NOTE The SIM registers can be written only in supervisor mode In user mode...

Page 1096: ...R See section 43 2 7 1104 4007_5060 Unique Identification Register Low SIM_UIDL 32 R See section 43 2 8 1104 4007_50EC Peripheral Clock Status Register SIM_PCSR 32 R 0000_0000h 43 2 9 1105 43 2 1 Sys...

Page 1097: ...y during VLPR and VLPW modes 1 USB voltage regulator in standby during VLPR and VLPW modes 28 18 Reserved This field is reserved This read only field is reserved and always has the value 0 17 16 Reser...

Page 1098: ...1 USBREGEN bit to be written This register bit clears after a write to USBREGEN 0 SOPT1 USBREGEN cannot be written 1 SOPT1 USBREGEN can be written Reserved This field is reserved This read only field...

Page 1099: ...silicon implementation number for the device 0001 Revision 1 1 11 7 DIEID Device Die Number Specifies the silicon implementation number for the device This field always reads as 11100 6 4 KEYATT Core...

Page 1100: ...lash Configuration Register 1 SIM_FCFG1 Address 4007_4000h base 104Ch offset 4007_504Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 PFSIZE 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12...

Page 1101: ...has the value 0 1 FLASHDOZE Flash Doze When set flash memory is disabled for the duration of Doze mode This field must be clear during VLP modes The flash will be automatically enabled again at the e...

Page 1102: ...ce specific value indicating amount of implemented flash SIM_FCFG2 field descriptions Field Description 31 Reserved This field is reserved This read only field is reserved and always has the value 0 3...

Page 1103: ...ed Reserved This field is reserved This read only field is reserved and always has the value 0 43 2 6 Unique Identification Register Mid High SIM_UIDMH Address 4007_4000h base 1058h offset 4007_5058h...

Page 1104: ...e Identification Unique identification for the device 43 2 8 Unique Identification Register Low SIM_UIDL Address 4007_4000h base 1060h offset 4007_5060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 1105: ...S2 CS1 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_PCSR field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 CS7 Cl...

Page 1106: ...Clock Status 0 Clock not ready 1 Clock ready 1 CS1 Clock Source 1 Clock Source 1 System Oscillator Status 0 Clock not ready 1 Clock ready 0 Reserved This field is reserved This read only field is rese...

Page 1107: ...ption and functionality of that mode This chapter describes all the available low power modes the sequence followed to enter exit each mode and the functionality available while in each of the modes T...

Page 1108: ...p modes are available that allow the state retention partial power down or full power down of certain logic and or memory I O states are held in all modes of operation Several registers are used to co...

Page 1109: ...s clocks are gated off after all stop acknowledge signals from supporting peripherals are valid The MCU is placed in a low leakage mode by powering down the internal logic and the system RAM2 partitio...

Page 1110: ...010 Stop Control Register SMC_STOPCTRL 32 R W 0000_0003h 44 3 5 1116 4007_E014 Power Mode Status register SMC_PMSTAT 32 R 44 3 6 1117 44 3 1 SMC Version ID Register SMC_VERID Address 4007_E000h base 0...

Page 1111: ...reserved and always has the value 0 7 Reserved This field is reserved This read only field is reserved and always has the value 0 6 EVLLS0 Existence of VLLS0 feature This static bit states whether or...

Page 1112: ...f the low power run or stop mode occurs by configuring the Power Mode Control register PMCTRL The PMPROT register can be written only once after any system reset If the MCU is configured for a disallo...

Page 1113: ...llows the MCU to enter any very low power mode VLPR VLPW and VLPS 0 VLPR VLPW and VLPS are not allowed 1 VLPR VLPW and VLPS are allowed 4 Reserved This field is reserved This read only field is reserv...

Page 1114: ...s 4007_E000h base Ch offset 4007_E00Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 RUNM 0 STOPA STOPM...

Page 1115: ...the previous stop mode entry sequence preventing the system from entering that mode This field is cleared by reset or by hardware at the beginning of any stop mode entry sequence and is set if the seq...

Page 1116: ...is field is reserved This read only field is reserved and always has the value 0 7 6 PSTOPO Partial Stop Option These bits control whether a Partial Stop mode is entered when STOPM STOP When entering...

Page 1117: ...f PMCTRL STOPM VLLSx reserved if PMCTRL STOPM LLSx 010 VLLS2 if PMCTRL STOPM VLLSx LLS2 if PMCTRL STOPM LLSx 011 VLLS3 if PMCTRL STOPM VLLSx LLS3 if PMCTRL STOPM LLSx 100 Reserved 101 Reserved 110 Res...

Page 1118: ...t sequence is complete 0000_0001 Current power mode is RUN 0000_0010 Current power mode is STOP 0000_0100 Current power mode is VLPR 0000_1000 Current power mode is VLPW 0001_0000 Current power mode i...

Page 1119: ...able 44 2 Power mode transition triggers Transition From To Trigger conditions 1 RUN WAIT Sleep now or sleep on exit modes entered with SLEEPDEEP clear controlled in System Control Register in Arm cor...

Page 1120: ...led in System Control Register in Arm core See note 1 VLPW VLPR Interrupt 5 VLPW RUN Reset 6 VLPR VLPS PMCTRL STOPM 0003 or 010 Sleep now or sleep on exit modes entered with SLEEPDEEP set which is con...

Page 1121: ...entered directly from RUN hardware will not allow this transition and will force exit back to RUN 12 RUN HSRUN Set PMPROT AHSRUN 1 PMCTRL RUNM 11 HSRUN RUN Set PMCTRL RUNM 00 or Reset 1 If debug is e...

Page 1122: ...PU executing the WFI instruction After the instruction is executed the following sequence occurs 1 The CPU clock is gated off immediately 2 Requests are made to all non CPU bus masters to enter Stop m...

Page 1123: ...completely entering the stop mode An aborted entry is possible only if the interrupt occurs before the PMC begins the transition to stop mode regulation After this point the interrupt is ignored until...

Page 1124: ...is put into a stop mode regulation state In this state the regulator is designed to supply enough current to the MCU over a reduced frequency To further reduce power in this mode disable the clocks t...

Page 1125: ...tion state but with a slightly elevated voltage output In this state the MCU is able to operate at a faster frequency compared to normal RUN mode For the maximum allowable frequencies see the Power Ma...

Page 1126: ...mode is entered by entering the Sleep Now or Sleep On Exit mode while SLEEPDEEP is cleared and the device is in VLPR mode In VLPW the on chip voltage regulator remains in its stop regulation state In...

Page 1127: ...ow Leakage Stop VLLSx 44 4 5 1 STOP mode STOP mode is entered via the sleep now or sleep on exit with the SLEEPDEEP bit set in the System Control Register in the Arm core The SCG module can be configu...

Page 1128: ...44 4 5 3 Low Leakage Stop LLSx modes This device contains two Low Leakage Stop modes LLS3 and LLS2 LLS or LLSx is often used in this document to refer to both modes All LLS modes can be entered from...

Page 1129: ...ed from normal RUN or VLPR modes The MCU enters the configured VLLS mode if In Sleep Now or Sleep On Exit mode the SLEEPDEEP bit is set in the System Control Register in the Arm core and The device is...

Page 1130: ...ode controller drives a corresponding acknowledge for each signal that is both CDBGPWRUPACK and CSYSPWRUPACK When both requests are asserted the mode controller handles attempts to enter STOP and VLPS...

Page 1131: ...es all debug IP and then asserts the VLLDBGACK control bit to allow the RCM to release the Arm core from reset and allow CPU operation to begin The VLLDBGACK bit is cleared by the debugger or can be l...

Page 1132: ...Functional description K32 L2A Reference Manual Rev 2 01 2020 1132 NXP Semiconductors...

Page 1133: ...00_0000h 45 2 1 1133 4007_C00C Register file register RFSYS_REG3 32 R W 0000_0000h 45 2 1 1133 4007_C010 Register file register RFSYS_REG4 32 R W 0000_0000h 45 2 1 1133 4007_C014 Register file registe...

Page 1134: ...ld descriptions Field Description 31 24 HH High higher byte 23 16 HL High lower byte 15 8 LH Low higher byte LL Low lower byte Memory Map and Registers K32 L2A Reference Manual Rev 2 01 2020 1134 NXP...

Page 1135: ...eries 46 1 1 TPM Philosophy The TPM is built upon a very simple timer HCS08 Timer PWM Module TPM used for many years on NXP s 8 bit microcontrollers The TPM extends the functionality to support operat...

Page 1136: ...tionally reset or cause the counter to start incrementing The counter can also optionally stop incrementing on counter overflow Support the generation of hardware triggers when the counter overflows a...

Page 1137: ...e logic channel N input CNV CHNIE CHNF channel N interrupt channel N output signal output modes logic generation of channel N outputs signals in output compare EPWM and CPWM modes generation of channe...

Page 1138: ...Register TPM2_VERID 32 R 0500_0007h 46 3 1 1141 4002_E004 Parameter Register TPM2_PARAM 32 R See section 46 3 2 1141 4002_E008 TPM Global Register TPM2_GLOBAL 32 R W 0000_0000h 46 3 3 1142 4002_E010 S...

Page 1139: ...000_0000h 46 3 4 1143 400A_C014 Counter TPM0_CNT 32 R W 0000_0000h 46 3 5 1144 400A_C018 Modulo TPM0_MOD 32 R W 0000_FFFFh 46 3 6 1145 400A_C01C Capture and Compare Status TPM0_STATUS 32 R W 0000_0000...

Page 1140: ...atus and Control TPM1_C1SC 32 R W 0000_0000h 46 3 8 1147 400A_D02C Channel n Value TPM1_C1V 32 R W 0000_0000h 46 3 9 1149 400A_D030 Channel n Status and Control TPM1_C2SC 32 R W 0000_0000h 46 3 8 1147...

Page 1141: ...eature set with Filter and Combine registers implemented 0x0007 Standard feature set with Filter Combine and Quadrature registers implemented 46 3 2 Parameter Register TPMx_PARAM Address Base address...

Page 1142: ...riptions Field Description 31 2 Reserved This field is reserved This read only field is reserved and always has the value 0 1 RST Software Reset Reset all internal logic and registers except the Globa...

Page 1143: ...ed This read only field is reserved and always has the value 0 8 DMA DMA Enable Enables DMA transfers for the overflow flag 0 Disables DMA transfers 1 Enables DMA transfers 7 TOF Timer Overflow Flag S...

Page 1144: ...disabled 01 TPM counter increments on every TPM counter clock 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock 11 TPM counter increments on rising edge of...

Page 1145: ...MOD Register Update Additional writes to the MOD write buffer are ignored until the register has been updated It is recommended to initialize the TPM counter write to CNT before writing to the MOD reg...

Page 1146: ...ress 1Ch offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 TOF 0 CH5F CH4F CH3F CH2F CH1F CH0F W w1c...

Page 1147: ...0 Flag See the register description 0 No channel event has occurred 1 A channel event has occurred 46 3 8 Channel n Status and Control TPMx_CnSC CnSC contains the channel interrupt status flag and co...

Page 1148: ...WM High true pulses clear Output on match up set Output on match down 01 Low true pulses set Output on match up clear Output on match down Address Base address 20h offset 8d i where i 0d to 5d Bit 31...

Page 1149: ...l not change state until acknowledged in the TPM counter clock domain 3 ELSB Edge or Level Select The functionality of ELSB and ELSA depends on the channel mode When a channel is disabled this field w...

Page 1150: ...its used to configure the combine channel modes for each pair of channels n and n 1 where n is all the even numbered channels Address Base address 64h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 1151: ...nnels 2 and 3 Enables the combine feature for channels 2 and 3 In input capture mode the combined channels use the even channel input In software compare modes the even channel match asserts the outpu...

Page 1152: ...put for output compare and PWM 4 TRIG4 Channel 4 Trigger 0 No effect 1 The input trigger is used for input capture and modulates output for output compare and PWM 3 TRIG3 Channel 3 Trigger 0 No effect...

Page 1153: ...POL5 Channel 5 Polarity 0 The channel polarity is active high 1 The channel polarity is active low 4 POL4 Channel 4 Polarity 0 The channel polarity is active high 1 The channel polarity is active low...

Page 1154: ...tput The filter delay is disabled when the value is zero otherwise the filter delay is configured as CH4FVAL 4 clock cycles 15 12 CH3FVAL Channel 3 Filter Value Selects the filter value for the channe...

Page 1155: ...R QUADEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPMx_QDCTRL field descriptions Field Description 31 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 QUA...

Page 1156: ...TPM counter direction and can only be used for software compare The quadrature decoder mode has precedence over the other modes 0 Quadrature decoder mode is disabled 1 Quadrature decoder mode is enab...

Page 1157: ...anged when the TPM counter is disabled 0 Trigger is active high 1 Trigger is active low 21 20 Reserved This field is reserved This read only field is reserved and always has the value 0 19 CPOT Counte...

Page 1158: ...dic interruptor DMA request using the Modulo register and timer overflow flag 0 All channels use the internally generated TPM counter as their timebase 1 All channels use an externally generated globa...

Page 1159: ...e The CMOD 1 0 bits in the SC register either disable the TPM counter or select one of two possible clock modes for the TPM counter After any reset CMOD 1 0 0 0 so the TPM counter is disabled The CMOD...

Page 1160: ...that is used by the channels either for input or output modes The counter updates from the selected clock divided by the prescaler The TPM counter has these modes of operation up counting see Up count...

Page 1161: ...4 3 2 Up down counting Up down counting is selected when SC CPWMS 1 When configured for up down counting configuring CONF MOD to less than 2 is not supported The value of 0 is loaded into the TPM cou...

Page 1162: ...al TPM counter is not generating the global time base then it can be used as an independent counter or pulse accumulator The local TPM counter can also be configured to synchronize to the global time...

Page 1163: ...ture channel sources When CSOT 1 the counter will only start incrementing on a rising edge on the channel input provided ELSnA 1 When CROT 1 the counter will reset to zero on either edge of the channe...

Page 1164: ...with programmable position polarity duration and frequency When the counter matches the value in the CnV register of an output compare channel the channel n output can be set cleared or toggled if MS...

Page 1165: ...nnel output channel n output CHnF bit TOF bit CNT MOD 0x0005 CnV 0x0003 counter overflow channel n match counter overflow channel n match counter overflow 0 1 2 3 4 5 0 1 2 3 4 5 0 1 previous value pr...

Page 1166: ...ches the value in the CnV register the CHnF bit is set and the channel n interrupt is generated if CHnIE 1 however the channel n output is not controlled by TPM If ELSnB ELSnA 1 0 then the channel n o...

Page 1167: ...d by 2 MOD see the following figure MOD must be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results In the CPWM mode the TPM counter counts up until i...

Page 1168: ...the following figure TOF bit 7 8 8 7 7 7 6 6 6 5 5 5 4 4 3 3 2 2 1 0 1 previous value CNT channel n output counter overflow channel n match in down counting channel n match in up counting channel n ma...

Page 1169: ...nnel n 1 interrupt is generated if CH n 1 IE 1 at the channel n 1 match TPM counter C n 1 V If channel n ELSnB ELSnA X 1 then the channel n output is forced low at the beginning of the period TPM coun...

Page 1170: ...ter channel n output with ELSnB ELSnA X 1 channel n output with ELSnB ELSnA 1 0 MOD C n V Zero C n 1 V Figure 46 16 Channel n output if C n V MOD and C n 1 V MOD and C n V C n 1 V TPM counter channel...

Page 1171: ...annel n output with ELSnB ELSnA 1 0 100 duty cycle MOD Zero C n 1 V C n V Figure 46 19 Channel n output if C n V MOD and C n 1 V MOD and C n V C n 1 V TPM counter C n V C n 1 V Zero channel n output w...

Page 1172: ...chronizer Filter Combine input capture logic is filter enabled TPM counter channel n interrupt channel n 1 interrupt C n 1 V C n V CH n 1 IE CH n 1 F CH n IE CH n F ELS n B ELS n A ELS n 1 B ELS n 1 A...

Page 1173: ...n B ELS n A 0 1 or 1 0 ELS n 1 B ELS n 1 A 0 1 or 1 0 46 4 10 Input Capture Filter The input capture filter function is only in input capture mode or in software compare mode when quadrature decoder m...

Page 1174: ...output counter clock divided by 4 Time Figure 46 24 Channel input filter example 46 4 11 Deadtime insertion The deadtime insertion is enabled in PWM combine modes when CHnFVAL is non zero The deadtim...

Page 1175: ...counter channel n 1 match channel n output before deadtime insertion channel n 1 output before deadtime insertion channel n output after deadtime insertion channel n 1 output after deadtime insertion...

Page 1176: ...he TPM counter is clocked by the channel 0 and channel 1 input signals when quadrature decoder mode is selected Therefore In quadrature decoder mode channel 0 and channel 1 can only be used in softwar...

Page 1177: ...happens when there is a rising edge at channel 0 signal and channel 1 signal is at logic zero there is a rising edge at channel 1 signal and channel 0 signal is at logic one there is a falling edge at...

Page 1178: ...TPM counter overflow occurred channel 0 channel 1 TPM counter increment decrement TPM counter MOD 0x0000 Time 1 1 1 1 1 1 1 set TOF set TOFDIR set TOF set TOFDIR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figu...

Page 1179: ...e is not CPWM then MOD register is updated after MOD register was written and the TPM counter changes from MOD to zero If the selected mode is CPWM then MOD register is updated after MOD register was...

Page 1180: ...erated if CHnF TOF 1 1 0 The channel overflow DMA transfer request is generated if CHnF TOF 1 The channel overflow interrupt is not generated 1 1 The channel overflow DMA transfer request is generated...

Page 1181: ...d negates at the same time as the pre trigger negation 46 4 16 Reset Overview The TPM is reset whenever any chip reset occurs When the TPM exits from reset the TPM counter and the prescaler counter ar...

Page 1182: ...Functional description K32 L2A Reference Manual Rev 2 01 2020 1182 NXP Semiconductors...

Page 1183: ...ipheral trigger inputs 000000 0x00 Trigger function is disabled 000001 0x01 Port pin trigger input is selected 000010 0x02 FlexIO Timer 0 input is selected 000011 0x03 FlexIO Timer 1 input is selected...

Page 1184: ...cted 011111 0x1F LPSPI0 RX data is selected 100000 0x20 LPSPI1 Frame is selected 100001 0x21 LPSPI1 RX data is selected 100010 0x22 RTC Seconds Counter is selected 100011 0x23 RTC Alarm is selected 10...

Page 1185: ...pplicable to all instances of TRGMUX For more details on the registers supported on each module instance please refer to The TRGMUX as implemented on the chip Table 47 1 TRGMUX Memory Map Offset Regis...

Page 1186: ...2 1 2 4 Fields Field Function 31 LK This bit shows whether the register can be written or not 0 Register can be written 1 Register cannot be written until the next system Reset 30 This read only bit f...

Page 1187: ...s reserved and always has the value 0 5 0 SEL0 This read write bit field is used to configure the MUX select for peripheral trigger input 0 Refer to the Select Bit Fields table in the Features section...

Page 1188: ...2 Refer to the Select Bit Fields table in the Features section for bit field information 15 14 This read only bit field is reserved and always has the value 0 13 8 SEL1 This read write bit field is us...

Page 1189: ...e 0 21 16 SEL2 This read write bit field is used to configure the MUX select for peripheral trigger input 2 Refer to the Select Bit Fields table in the Features section for bit field information 15 14...

Page 1190: ...read only bit field is reserved and always has the value 0 29 24 This read only bit field is reserved and always has the value 0 23 22 This read only bit field is reserved and always has the value 0 2...

Page 1191: ...0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved SEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47 2 1 6 3 Fields Field Function 31 LK This bit shows whether the...

Page 1192: ...gger input 0 Refer to the Select Bit Fields table in the Features section for bit field information 47 2 1 7 TRGMUX LPI2C2 TRGMUX_LPI2C2 47 2 1 7 1 Address Register Offset TRGMUX_LPI2C2 4002701Ch TRGM...

Page 1193: ...always has the value 0 15 14 This read only bit field is reserved and always has the value 0 13 8 This read only bit field is reserved and always has the value 0 7 6 This read only bit field is reser...

Page 1194: ...s read only bit field is reserved and always has the value 0 23 22 This read only bit field is reserved and always has the value 0 21 16 This read only bit field is reserved and always has the value 0...

Page 1195: ...gister cannot be written until the next system Reset 30 This read only bit field is reserved and always has the value 0 29 24 This read only bit field is reserved and always has the value 0 23 22 This...

Page 1196: ...0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved SEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47 2 1 10 3 Fields Field Function 31 LK This bit shows whether the...

Page 1197: ...gger input 0 Refer to the Select Bit Fields table in the Features section for bit field information 47 2 1 11 TRGMUX DAC0 TRGMUX_DAC0 47 2 1 11 1 Address Register Offset TRGMUX_DAC0 40027034h TRGMUX R...

Page 1198: ...elect for peripheral trigger input 0 Refer to the Select Bit Fields table in the Features section for bit field information 47 2 2 TRGMUX Register Descriptions These register may not be applicable to...

Page 1199: ...ion TRGMUX Register 47 2 2 2 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R LK Rese rved Reserved Reserved SEL2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6...

Page 1200: ...trigger input 1 Refer to the Select Bit Fields table in the Features section for bit field information 7 6 This read only bit field is reserved and always has the value 0 5 0 SEL0 This read write bit...

Page 1201: ...bit field information 15 14 This read only bit field is reserved and always has the value 0 13 8 SEL1 This read write bit field is used to configure the MUX select for peripheral trigger input 1 Refe...

Page 1202: ...s read only bit field is reserved and always has the value 0 21 16 SEL2 This read write bit field is used to configure the MUX select for peripheral trigger input 2 Refer to the Select Bit Fields tabl...

Page 1203: ...Register cannot be written until the next system Reset 30 This read only bit field is reserved and always has the value 0 29 24 This read only bit field is reserved and always has the value 0 23 22 Th...

Page 1204: ...0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved SEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47 2 2 6 3 Fields Field Function 31 LK This bit shows whether th...

Page 1205: ...ger input 0 Refer to the Select Bit Fields table in the Features section for bit field information 47 2 2 7 TRGMUX LPI2C0 TRGMUX_LPI2C0 47 2 2 7 1 Address Register Offset TRGMUX_LPI2C0 400A701Ch TRGMU...

Page 1206: ...nd always has the value 0 15 14 This read only bit field is reserved and always has the value 0 13 8 This read only bit field is reserved and always has the value 0 7 6 This read only bit field is res...

Page 1207: ...ad only bit field is reserved and always has the value 0 23 22 This read only bit field is reserved and always has the value 0 21 16 This read only bit field is reserved and always has the value 0 15...

Page 1208: ...Register cannot be written until the next system Reset 30 This read only bit field is reserved and always has the value 0 29 24 This read only bit field is reserved and always has the value 0 23 22 T...

Page 1209: ...0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved SEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47 2 2 10 3 Fields Field Function 31 LK This bit shows whether the...

Page 1210: ...eserved and always has the value 0 7 6 This read only bit field is reserved and always has the value 0 5 0 SEL0 This read write bit field is used to configure the MUX select for peripheral trigger inp...

Page 1211: ...to guess or predict It is important that a random number is at least as difficult to predict as it is difficult to break the cryptographic algorithm with which it is being used This stringent requirem...

Page 1212: ...random noise within the device in which the TRNG is used This noise causes various small changes in the period of the oscillator Therefore if the count of the ring oscillator clock cycles is sampled a...

Page 1213: ...ation Run a self test on the TRNG to assure proper continued operation This involves taking TRNG off line setting some self test parameters running TRNG and then reading the statistical test registers...

Page 1214: ...int_b is asserted when MCTL ENT_VAL 1 After the polling completes the 512 bit entropy generated by the TRNG can be read The values can be read in any order from entropy register 0 to register 15 ENT0...

Page 1215: ...esses defined in the memory map below Although many of the TRNG0 registers hold more than 32 bits the register addresses shown in the Memory Map below represent how these registers are accessed over t...

Page 1216: ...C 32 RO 00000000h 400A502Ch TRNG0 Statistical Check Run Length 3 Limit TRNG0_SCR3L 32 RW 0058007Dh 400A5030h TRNG0 Statistical Check Run Length 4 Count TRNG0_SCR4C 32 RO 00000000h 400A5030h TRNG0 Stat...

Page 1217: ...RNG0_MCTL 400A5000h 48 1 3 3 2 2 Function This register is intended to be used for programming configuring and testing the RNG It is the main register to read write in order to enable Entropy generati...

Page 1218: ...If the TRNG0 clock is stopped while the TRNG ring oscillator is running the oscillator will continue running even though the TRNG0 clock is stopped TSTOP_OK is asserted when the TRNG ring oscillator...

Page 1219: ...RGM bit is being written to 1 simultaneously to writing this field This field is cleared to the default POR value by writing the RST_DEF bit to 1 00 use ring oscillator with no divide 01 use ring osci...

Page 1220: ...ble only if TRNG0_MCTL PRGM bit is 1 This field will read zeroes if TRNG0_MCTL PRGM 0 This field is cleared to the default POR value by writing the TRNG0_MCTL RST_DEF bit to 1 15 8 Reserved 7 0 LRUN_M...

Page 1221: ...a Poker Test is run which requires a maximum and minimum limit The maximum is programmed in the PKRMAX PKR_MAX register and the minimum is derived by subtracting the PKR_RNG value from the programmed...

Page 1222: ...maximum and minimum limit The maximum allowable result is programmed in the TRNG0_PKRMAX PKR_MAX register This field is writable only if TRNG0_MCTL PRGM bit is 1 This register is cleared to the defau...

Page 1223: ...Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PKR_SQ W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 1 3 3 6 4 Fields Field Function 31 24 23 0 PKR_SQ Poker Square Cal...

Page 1224: ...1 3 3 7 4 Fields Field Function 31 16 ENT_DLY Entropy Delay Defines the length in system clocks of each Entropy sample taken This field is writable only if TRNG0_MCTL PRGM bit is 1 This field will rea...

Page 1225: ...rved SB_LIM W Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 48 1 3 3 8 4 Fields Field Function 31 10 Reserved Always 0 9 0 SB_LIM Sparse Bit Limit During Von Neumann sampling if enabled by TRNG0_MCTL SAMP_MOD...

Page 1226: ...Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved TOT_SAM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TOT_SAM W Reset 0 0 0 0 0 0 0 0 0...

Page 1227: ...m Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved FRQ_MIN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FRQ_MIN W Reset 0 0 0 0 0 1 1 0 0 1 0 0 0...

Page 1228: ...9 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved FRQ_CT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FRQ_CT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 1 3 3...

Page 1229: ...0_FRQCNT readback register 48 1 3 3 12 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved FRQ_MAX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 1230: ...this offset is used as TRNG0_SCMC readback register as described here 48 1 3 3 13 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit...

Page 1231: ...zero If the Retry Count has reached zero an error will be generated Note that this offset 0x20 is used as TRNG0_SCML only if TRNG0_MCTL PRGM is 1 If TRNG0_MCTL PRGM is 0 this offset is used as TRNG0_S...

Page 1232: ...ad the final Run Length 1 counts after entropy generation These counters start with the value in TRNG0_SCRxC1L RUN1_MAX The R1_1_CT decrements each time a single one is sampled preceded by a zero and...

Page 1233: ...l Check Run Length 1 Limit Register defines the allowable maximum and minimum number of runs of length 1 detected during entropy generation To pass the test the number of runs of length 1 for samples...

Page 1234: ...1 detected during entropy generation The number of runs of length 1 detected during entropy generation must be less than RUN1_MAX else a retry or error will occur This register is cleared to the defau...

Page 1235: ...set 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 1 3 3 17 4 Fields Field Function 31 30 Reserved Always 0 29 16 R2_1_CT Runs of One Length 2 Count Reads the final Runs of Ones length 2 count after entropy gener...

Page 1236: ...17 16 R Reserved RUN2_RNG W Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved RUN2_MAX W Reset 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 48 1 3 3 18 4 Fields Field Fun...

Page 1237: ...led preceded by a one and followed by a one Note that this offset 0x2C is used as TRNG0_SCRxC3L if TRNG0_MCTL PRGM is 1 If TRNG0_MCTL PRGM is 0 this offset is used as TRNG0_SCRxC3C readback register a...

Page 1238: ...s than the programmed maximum value and the number of runs of length 3 must be greater than maximum range If this test fails the Retry Counter in TRNG0_SCMISC will be decremented and a retry will occu...

Page 1239: ...it to 1 48 1 3 3 21 TRNG0 Statistical Check Run Length 4 Count TRNG0_SCR4C 48 1 3 3 21 1 Address Register Offset Description TRNG0_SCR4C 400A5030h Accessible at this address when TRNG0_MCTL PRGM 0 48...

Page 1240: ...ation Requires TRNG0_MCTL PRGM 0 48 1 3 3 22 TRNG0 Statistical Check Run Length 4 Limit TRNG0_SCR4L 48 1 3 3 22 1 Address Register Offset Description TRNG0_SCR4L 400A5030h Accessible at this address w...

Page 1241: ...oth 0 and 1 detected during entropy generation must be greater than RUN4_MAX RUN4_RNG else a retry or error will occur This register is cleared to the default POR value by writing the TRNG0_MCTL RST_D...

Page 1242: ...register as described here 48 1 3 3 23 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved R5_1_CT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 1243: ...ed Note that this address 0x34 is used as TRNG0_SCRxC5L only if TRNG0_MCTL PRGM is 1 If TRNG0_MCTL PRGM is 0 this address is used as TRNG0_SCRxC5C readback register 48 1 3 3 24 3 Diagram Bits 31 30 29...

Page 1244: ...ead the final Run Length 6 counts after entropy generation These counters start with the value in TRNG0_SCRxC6PL RUN6P_MAX The R6P_1_CT decrements each time six or more consecutive ones are sampled pr...

Page 1245: ...Run Length 6 Limit Register defines the allowable maximum and minimum number of runs of length 6 or more detected during entropy generation To pass the test the number of runs of length 6 or more for...

Page 1246: ...is register is cleared to the default POR value by writing the TRNG0_MCTL RST_DEF bit to 1 15 11 Reserved Always 0 10 0 RUN6P_MAX Run Length 6 Maximum Limit Defines the maximum allowable runs of lengt...

Page 1247: ...By default RETRY_CT is initialized to 1 but software can increase the retry count by writing to the RTY_CT field in the TRNG0_SCMISC register All 0s will be returned if this register address is read w...

Page 1248: ...un Sampling 1s Test has failed 6 TF4BR0 Test Fail 4 Bit Run Sampling 0s If TF4BR0 1 the 4 Bit Run Sampling 0s Test has failed 5 TF3BR1 Test Fail 3 Bit Run Sampling 1s If TF3BR1 1 the 3 Bit Run Samplin...

Page 1249: ...G0_MCTL ENT_VAL 1 After at most one 1 bus clock cycle of reading a valid TRNG0_ENT15 register value reading any TRNG0_ENT0 through TRNG0_ENT15 register would return zeroes 48 1 3 3 28 3 Diagram Bits 3...

Page 1250: ...ster is readable only if TRNG0_MCTL PRGM is 0 otherwise zeroes will be read 48 1 3 3 29 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PKR_1_CT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1251: ...this register is readable only if TRNG0_MCTL PRGM is 0 otherwise zeroes will be read 48 1 3 3 30 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PKR_3_CT W Reset 0 0 0 0 0 0 0 0 0 0 0...

Page 1252: ...ster is readable only if TRNG0_MCTL PRGM is 0 otherwise zeroes will be read 48 1 3 3 31 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PKR_5_CT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1253: ...this register is readable only if TRNG0_MCTL PRGM is 0 otherwise zeroes will be read 48 1 3 3 32 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PKR_7_CT W Reset 0 0 0 0 0 0 0 0 0 0 0...

Page 1254: ...ster is readable only if TRNG0_MCTL PRGM is 0 otherwise zeroes will be read 48 1 3 3 33 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PKR_9_CT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1255: ...this register is readable only if TRNG0_MCTL PRGM is 0 otherwise zeroes will be read 48 1 3 3 34 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PKR_B_CT W Reset 0 0 0 0 0 0 0 0 0 0 0...

Page 1256: ...ster is readable only if TRNG0_MCTL PRGM is 0 otherwise zeroes will be read 48 1 3 3 35 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PKR_D_CT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1257: ...ly if TRNG0_MCTL PRGM is 0 otherwise zeroes will be read 48 1 3 3 36 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PKR_F_CT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12...

Page 1258: ...Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved SK_V AL NO_P RGM SH0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 1 3 3 37 4 Fields Field Function 31 3 Reserved 2 SK_VAL Reserved DRNG specific not...

Page 1259: ...sert the corresponding bit in the status register Even if the interrupt is cleared or masked interrupt status information can be read from the TRNG0_MCTL register 48 1 3 3 38 3 Diagram Bits 31 30 29 2...

Page 1260: ...currently three important interrupts that are generated by the TRNG See TRNG0_INT_STATUS register description above Each interrupt can be masked disabled by de asserting the corresponding bit in the T...

Page 1261: ...d to control and provide status for the currently three important interrupts that are generated by the TRNG The ipi_rng_int_b interrupt signals that TRNG0 has either generated a Frequency Count Fail E...

Page 1262: ...t frequency errors 1 The frequency counter has detected a failure 1 ENT_VAL Read only Entropy Valid Will assert only if TRNG ACC bit is set and then after an entropy value is generated Will be cleared...

Page 1263: ...3 2 1 0 R TRNG0_MAJ_REV TRNG0_MIN_REV W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 48 1 3 3 41 4 Fields Field Function 31 16 TRNG0_IP_ID Shows the IP ID 0000000000110000 ID for TRNG 15 8 TRNG0_MAJ_ REV Sh...

Page 1264: ...31 24 TRNG0_ERA Shows the compile options for the TRNG 00000000 COMPILE_OPT for TRNG 23 16 TRNG0_INTG_ OPT Shows the integration options for the TRNG 00000000 INTG_OPT for TRNG 15 8 TRNG0_ECO_ REV Sh...

Page 1265: ...of scan or the conversion result is out of the range specified by TSI threshold It provides a solid capacitive measurement module to the implementation of touch keyboard rotaries and sliders 49 1 1 Fe...

Page 1266: ...y functional in this mode When a scan completes TSI submits an interrupt request to CPU if the interrupt is enabled Run TSI module is fully functional in this mode When a scan completes TSI submits an...

Page 1267: ...pad must be kept as short as possible to reduce distribution capacity on board 49 3 Register definition This section describes the memory map and control status registers for the TSI module TSI memory...

Page 1268: ...ld Description 31 OUTRGF Out of Range Flag This flag is set if the result register of the enabled electrode is out of the range defined by the TSI_THRESHOLD register This flag is set only when TSI is...

Page 1269: ...y limitation circuit is disabled 1000 Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is enabled to work in higher frequencies operations 1100 Set...

Page 1270: ...1 Twice per electrode 00010 3 times per electrode 00011 4 times per electrode 00100 5 times per electrode 00101 6 times per electrode 00110 7 times per electrode 00111 8 times per electrode 01000 9 ti...

Page 1271: ...us This read only bit indicates if scan is in progress This bit will get asserted after the analog bias circuit is stable after a trigger and it changes automatically by the TSI 0 No scan in progress...

Page 1272: ...TSICH 0 DMAEN 0 0 W SWTS Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TSICNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSIx_DATA field descriptions Field Descriptio...

Page 1273: ...1 to this bit will start a scan The electrode channel to be scanned is determinated by TSI_DATA TSICH bits 0 No effect 1 Start a scan to determine which channel is specified by TSI_DATA TSICH 21 16 Re...

Page 1274: ...al to the time 49 4 1 1 TSI electrode oscillator The TSI electrode oscillator circuit is illustrated in the following figure A configurable constant current source is used to charge and discharge the...

Page 1275: ...a current source of I 16 A and V 600 m V have the following oscillation frequency Felec 16 A 2 20pF 600mV 0 67MHz Equation 5 TSI electrode oscillator frequency The current source is used to accommoda...

Page 1276: ...source of I 16 A and V 600 mV PS 2 and NSCN 16 have the following sampling time Tcap_samp 2 2 16 20pF 600mV 16 A 48 s 49 4 1 3 TSI reference oscillator The TSI reference oscillator has the same topol...

Page 1277: ...l in run wait and low power modes The TSI_GENCS TSIEN bit must be set to enable the TSI module in run and wait mode When TSI_GENCS STPE bit is set it allows the TSI module to work in low power mode 49...

Page 1278: ...ease refer to the Current source for more details The output of electrode oscillator has several prescalers up to 128 indicated by TSI_GENCS PS This allows a flexible counter configuration for differe...

Page 1279: ...REFCHRG still control the corresponding current sources that is TSI_GENCS EXTCHRG controls the reference oscillator current and TSI_GENCS REFCHRG controls the electrode oscillator current 49 4 9 End...

Page 1280: ...and TSI_GENCS TSIIE TSI can bring MCU out of its low power modes STOP VLPS VLLS etc by either end of scan or out of range interrupt that is if TSI_GENCS ESOR is set end of scan interrupt is selected a...

Page 1281: ...The threshold for this amplitude detection is set by DVOLT register bits Also the external voltage is biased by vmid voltage with a Rs series resistance The vmid voltage is defined as V vmid V vp V vm...

Page 1282: ...se source external to the MCU It is possible to observe in the following figure that in noise detection mode the clkref output has the peak detection and the number of detected peaks can be counted or...

Page 1283: ...ernally by the module until the point that there is no noise voltage trepassing the threshold The following diagram shows how it is done The threshold comparator output goes to a counter and as the DV...

Page 1284: ...eset state EXTCHRG 0 In this operation mode this bits selects the series resistance 0 uses Rs 32 k 1 uses Rs 187 k Independent of this bit selection the threshold I 0 DVOLT 1 0 Select voltage rails of...

Page 1285: ...DE 3 2 01 or 10 Single thrshold noise mode operation I 00 DVOLT 1 0 EXTCHRG 2 1 In this operation mode these 4 bits are used select the noise threshold 0000 DVpm 0 038 V Vp 0 834 V Vm 0 796 V 0001 DVp...

Page 1286: ...V 1110 DVpm 1 630 V Vp 1 630 V Vm 0 V 1111 DVpm 1 630 V Vp 1 630 V Vm 0 V EXTCHRG 0 In this operation mode this bits selects the series resistance 0 uses Rs 32 k 1 uses Rs 187 k Independent of this bi...

Page 1287: ...ntains a 56 bit clock cycle counter which is reset by system reset NOTE The TSTMR registers can be read with 32 bit accesses only TSTMR memory map Absolute address hex Register name Width in bits Acce...

Page 1288: ...l zero reset value may not be readable because the value will increment before it can be read by the software 50 2 2 Time Stamp Timer Register High TSTMRx_H The Time Stamp Timer is a 56 bit counters c...

Page 1289: ...ion and can be read at any time by the software for determining the software ticks However the software must follow the read sequence as mentioned in the TSTMR register descriptions for correctly read...

Page 1290: ...Functional description K32 L2A Reference Manual Rev 2 01 2020 1290 NXP Semiconductors...

Page 1291: ...USB 2 0 Specification usb org 2008 The USB full speed controller interfaces to a USBFS LS transceiver NOTE This chapter describes the following registers that have similar names USB_OTGCTL USB_CTL USB...

Page 1292: ...attached configured used and detached while the host and other peripherals are in operation USB software provides a uniform view of the system for all application software hiding implementation detail...

Page 1293: ...nnect directly to a printer or a keyboard can connect to a tablet to exchange data With the USB On The Go product you can develop a fully USB compliant peripheral device that can also assume the role...

Page 1294: ...16 bidirectional endpoints DMA or FIFO data stream interfaces Low power consumption FIRC with clock recovery is supported to eliminate the 48 MHz crystal It is used for USB device only implementation...

Page 1295: ...also useful in Device mode as explained below NOTE For device operation the internal 15 k pulldowns should be enabled to keep the DP and DM ports in a known quiescent state when the VBUS detection so...

Page 1296: ...gulator 3 3v OUT IN USB connector Figure 51 3 Host only diagram USB_DM USB_DP VBUS D D GND VDD USBVDD 33 33 Place resistors close to the processor External 5v to 3 3v regulator 3 3v OUT IN MCU USB con...

Page 1297: ...rection requires two 8 byte Buffer Descriptor BD entries Therefore a system with 16 fully bidirectional endpoints would require 512 bytes of system memory to implement the BDT The two BD entries allow...

Page 1298: ...ains indirect address pointers to where the actual buffer resides in system memory This indirect address mechanism is shown in the following diagram Current Endpoint BDT Buffer in Memory BDT Page Star...

Page 1299: ...to the starting location of the BDT The BDT must be located on a 512 byte boundary in system memory All enabled TX and RX endpoint BD entries are indexed into the BDT to allow easy access via USBFS o...

Page 1300: ...red in the BDs to determine Who owns the buffer in system memory Data0 or Data1 PID Whether to release ownership upon packet completion No address increment FIFO mode Whether data toggle synchronizati...

Page 1301: ...rocessor is not informed that a token has been processed the data is simply transferred to or from the FIFO When KEEP is set normally the NINC bit is also set to prevent address increment 0 Allows USB...

Page 1302: ...USBOTG to issue a STALL handshake for both directions of the associated endpoint To clear the stall condition 1 Clear the associated USB_ENDPTn EPSTALL bit 2 Write the BDT to clear OWN and BDT_STALL...

Page 1303: ...then processes the last BD The following figure shows a timeline of how a typical USB token is processed after the BDT is read and OWN 1 SETUP TOKEN DATA ACK USB RST SOF IN TOKEN DATA ACK OUT TOKEN D...

Page 1304: ...ode the TOKDNE interrupt is generated and the TOK_PID field of the BDT is 1111 to indicate the DMA latency error Host mode software can decide to retry or move to next scheduled item In device mode th...

Page 1305: ...L 8 R W 00h 51 4 17 1320 4005_50A4 Frame Number register High USB0_FRMNUMH 8 R W 00h 51 4 18 1321 4005_50A8 Token register USB0_TOKEN 8 R W 00h 51 4 19 1321 4005_50AC SOF Threshold register USB0_SOFTH...

Page 1306: ...W 00h 51 4 23 1324 4005_5100 USB Control register USB0_USBCTRL 8 R W C0h 51 4 24 1325 4005_5104 USB OTG Observe register USB0_OBSERVE 8 R 50h 51 4 25 1326 4005_5108 USB OTG Control register USB0_CONT...

Page 1307: ...is field always reads 0x4h 51 4 2 Peripheral ID Complement register USBx_IDCOMP Reads back the complement of the Peripheral ID register For the USB peripheral the value is 0xFB Address 4005_5000h base...

Page 1308: ...ADDINFO Reads back the value of the Host Enable bit Address 4005_5000h base Ch offset 4005_500Ch Bit 7 6 5 4 3 2 1 0 Read 0 0 IEHOST Write Reset 0 0 0 0 0 0 0 1 USBx_ADDINFO field descriptions Field D...

Page 1309: ...ts 5 LINE_STATE_ CHG This interrupt is set when the USB line state CTL SE0 and CTL JSTATE bits are stable without change for 1 millisecond and the value of the line state is different from the last ti...

Page 1310: ...interrupt 1 Enables the 1ms timer interrupt 5 LINESTATEEN Line State Change Interrupt Enable 0 Disables the LINE_STAT_CHG interrupt 1 Enables the LINE_STAT_CHG interrupt 4 Reserved This field is reser...

Page 1311: ...estate in detection of Connect Disconnect and Resume signaling First read LINE_STATE_CHG field and then read this field If this field reads as 1 then the value of LINE_STATE_CHG can be considered stab...

Page 1312: ...th bit 4 DMLOW 0 D pulldown resistor is not enabled 1 D pulldown resistor is enabled 4 DMLOW D Data Line pull down resistor enable 0 D pulldown resistor is not enabled 1 D pulldown resistor is enabled...

Page 1313: ...y valid if CTL HOSTMODEEN 1 This interrupt signifies that a peripheral is now present and must be configured it is asserted if there have been no transitions on the USB for 2 5 s and the current bus s...

Page 1314: ...STAT register This register contains the value of 0x00 after a reset Address 4005_5000h base 84h offset 4005_5084h Bit 7 6 5 4 3 2 1 0 Read STALLEN ATTACHEN RESUMEEN SLEEPEN TOKDNEEN SOFTOKEN ERROREN...

Page 1315: ...r 6 OWNERR This field is valid when the USB Module is operating in peripheral mode CTL HOSTMODEEN 0 It is set if the USB Module requires a new BD for SETUP ISO IN or ISO OUT transfer while a new BD is...

Page 1316: ...t is set when the PID check field fails 51 4 12 Error Interrupt Enable register USBx_ERREN Contains enable bits for each of the error interrupt sources within the USB module Setting any of these bits...

Page 1317: ...tion The data in the status register is valid when TOKDNE interrupt is asserted The Status register is actually a read window into a status FIFO maintained by the USB module When the USB module uses a...

Page 1318: ...The polarity of this signal is affected by the current state of LSEN 6 SE0 Live USB Single Ended Zero signal 5 TXSUSPENDTOKENBUSY In Host mode TOKEN_BUSY is set when the USB module is busy executing a...

Page 1319: ...ing SOF tokens 0 Disables the USB Module 1 Enables the USB Module 51 4 15 Address register USBx_ADDR Holds the unique USB address that the USB module decodes when in Peripheral mode CTL HOSTMODEEN 0 W...

Page 1320: ...eld Description 7 1 BDTBA Provides address bits 15 through 9 of the BDT base address 0 Reserved This field is reserved This read only field is reserved and always has the value 0 51 4 17 Frame Number...

Page 1321: ...al it writes the TOKEN type and endpoint to this register After this register has been written the USB module begins the specified USB transaction to the address contained in the address register The...

Page 1322: ...e times when SOFDYNTHLD 0 or 8 byte times when SOFDYNTHLD 1 before the SOF stops initiating token packet transactions This register must be set to a value that ensures that other packets are not activ...

Page 1323: ...through 16 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory 51 4 22 BDT Page Register 3 USBx_BDTPAGE3 Contains an 8 bit value used to compute the a...

Page 1324: ...PCTLDIS EPRXEN and EPTXEN define if an endpoint is enabled and define the direction of the endpoint The endpoint enable direction control is defined in the following table Table 51 7 Endpoint enable a...

Page 1325: ...sfers See Table 51 7 1 EPSTALL When set this bit indicates that the endpoint is stalled This bit has priority over all other control bits in this register but it is only valid if EPTXEN 1 or EPRXEN 1...

Page 1326: ...base 104h offset 4005_5104h Bit 7 6 5 4 3 2 1 0 Read DPPU DPPD 0 DMPD 0 Write Reset 0 1 0 1 0 0 0 0 USBx_OBSERVE field descriptions Field Description 7 DPPU Provides observability of the D Pullup ena...

Page 1327: ...ways has the value 0 51 4 27 USB Transceiver Control register 0 USBx_USBTRC0 Includes signals for basic operation of the on chip USB Full Speed transceiver and configuration of the USB data connection...

Page 1328: ...y be enabled when the Transceiver is suspended 4 VFEDG_DET VREGIN Falling Edge Interrupt Detect Use USBx_MISCCTRL VFEDG_EN to enable this bitfield 0 VREGIN falling edge interrupt has not been detected...

Page 1329: ...5_5000h base 12Ch offset 4005_512Ch Bit 7 6 5 4 Read 0 VFEDG_EN Write Reset 0 0 0 0 Bit 3 2 1 0 Read VREDG_EN OWNERRISODIS SOFBUSSET SOFDYNTHLD Write Reset 0 0 0 0 USBx_MISCCTRL field descriptions Fie...

Page 1330: ...the clock extracted from the incoming USB data stream NOTE The FIRC must be enabled in the SCG module Address 4005_5000h base 140h offset 4005_5140h Bit 7 6 5 4 3 2 1 0 Read CLOCK_ RECOVER_ EN RESET_...

Page 1331: ...lue default 1 Trim fine restarts from the IFR trim value whenever bus_reset bus_resume is detected or module enable is desasserted 4 3 Reserved This field is reserved 2 Reserved This field is reserved...

Page 1332: ...Description 7 5 Reserved This field is reserved Should always be written as 0 4 OVF_ERROR_ EN Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT 0 The interrup...

Page 1333: ...ost controller found on PC motherboards Host mode allows bulk isochronous interrupt and control transfers Bulk data transfers are performed at nearly the full USB interface bandwidth Support is provid...

Page 1334: ...to suspend CTL USB_EN 1 7 Enumerate the attached device by sending the appropriate commands to the default control pipe of the connected device To complete a control transaction to a connected device...

Page 1335: ...en the data packet completes the BDT is written and a Token Done ISTAT DNE interrupt is asserted For control transfers with a single packet data phase this completes the data phase of the setup transa...

Page 1336: ...ates that one of the BDTs has been released back to the processor and the transfer has completed If the peripheral device asserts NAKs the USB FS continues to retry the transfer indefinitely without p...

Page 1337: ...device Go to B_IDLE If the A application wants to use the bus or if the B device is doing an SRP as indicated by an A_SESS_VLD Interrupt or Attach or Port Status Change Interrupt check data line for 5...

Page 1338: ...HNP enabled and B disconnects in 150 ms then B device is becoming the host Go to A_PERIPHERAL Turn off Host mode If A wants to start another session Go to A_HOST A_PERIPHERAL If ID Interrupt or if A_...

Page 1339: ...rrupt or SRP Done SRP must be done in less than 100 ms Go to B_IDLE B_PERIPHERAL If HNP enabled and the bus is suspended and B wants the bus the B device can become the host Go to B_WAIT_ACON Turn off...

Page 1340: ..._CLK_RECOVER_CTRL CLOCK_RECOVER_EN 1b 3 Choose the clock source of USB by configuring the muxes 4 The USB clock source must choose the output of the divided clock For chip specific details see the USB...

Page 1341: ...from an input power supply varying from 2 7 V to 5 5 V It consists of one 3 3 V power channel When the input power supply is below 3 6 V the regulator goes to pass through mode The following figure s...

Page 1342: ...enabled but a switch disconnects its output from the external pin In STANDBY mode the RUN regulator is disabled and the STANDBY regulator output is connected to the external pin Internal power mode si...

Page 1343: ...regulator is disabled and the standby regulator is active The switch connecting the STANDBY regulator output to the external pin is closed SHUTDOWN The module is disabled The regulator is enabled by...

Page 1344: ...USB Voltage Regulator Module Signal Descriptions K32 L2A Reference Manual Rev 2 01 2020 1344 NXP Semiconductors...

Page 1345: ...ternal devices or used internally in the device as a reference to analog peripherals such as the ADC DAC or CMP The Voltage Reference VREF can supply an accurate voltage output that can be trimmed in...

Page 1346: ...1 2V or 2 1V In addition the buffered reference is available internally for use with on chip peripherals such as ADCs and DACs Refer to the chip configuration details When the VREF is enabled the ref...

Page 1347: ...f it is desired to use the VREF regulator and or the chop oscillator in the very low power modes the system reference voltage also referred to as the bandgap voltage reference must be enabled in these...

Page 1348: ...1348 4007_2001 VREF Status and Control Register VREF_SC 8 R W 00h 53 2 2 1350 4007_2005 VREF Trim Register 4 VREF_TRM4 8 R W 00h 53 2 3 1351 53 2 1 VREF Trim Register VREF_TRM This register contains t...

Page 1349: ...also be enabled See the chip specific VREF information also known as chip configuration details to see how this can be achieved 0 Chop oscillator is disabled 1 Chop oscillator is enabled TRIM Trim bit...

Page 1350: ...a constant internal voltage supply in order to reduce the sensitivity to external supply noise and variation If it is desired to keep the regulator enabled in very low power modes refer to the Chip Co...

Page 1351: ...1 Reserved 53 2 3 VREF Trim Register 4 VREF_TRM4 This register contains the enable and trim for VREF 2 1V generation Address 4007_2000h base 5h offset 4007_2005h Bit 7 6 5 4 3 2 1 0 Read VREF2V1_ EN 0...

Page 1352: ...uired 1 10 Voltage Reference enabled low power buffer on VREF_OUT available for internal and external use 100 nF capacitor is required 1 11 Reserved Reserved 53 3 1 Voltage Reference Disabled SC VREFE...

Page 1353: ...onger of Tstup or until SC VREFST 1 when the chop oscillator is not enabled If the chop oscillator is being used you must wait the time specified by Tchop_osc_stup chop oscillator start up time to ens...

Page 1354: ...is not enabled When the chop oscillator is enabled the settling time of the internal bandgap reference is defined by Tchop_osc_stup chop oscillator start up time You must wait this time Tchop_osc_stu...

Page 1355: ...See section Internal voltage regulator for details on the required sequence to enable the internal regulator Chapter 53 Voltage Reference VREF K32 L2A Reference Manual Rev 2 01 2020 NXP Semiconductors...

Page 1356: ...Initialization Application Information K32 L2A Reference Manual Rev 2 01 2020 1356 NXP Semiconductors...

Page 1357: ...atures of the WDOG32 module include Configurable clock source inputs independent from the bus clock Bus clock slow clock LPO 1 kHz clock from PMC SIRC 8 MHz IRC from SCG ERCLK external reference clock...

Page 1358: ...configuration bits Software must make updates within 128 bus clocks after unlocking and before WDOG32 closes the unlock window 54 1 2 Block diagram The following figure shows a block diagram of the WD...

Page 1359: ...R W 0000_0000h 54 2 4 1363 54 2 1 Watchdog Control and Status Register WDOGx_CS This section describes the function of Watchdog Control and Status Register NOTE TST is cleared 0 0 on POR only Any othe...

Page 1360: ...prescalar enabled 11 10 Reserved This field is reserved This read only field is reserved and always has the value 0 9 8 CLK Watchdog Clock This write once field indicates the clock source that feeds...

Page 1361: ...enabled only the low byte is used CNT CNTLOW is compared with TOVAL TOVALLOW 11 Watchdog test mode enabled only the high byte is used CNT CNTHIGH is compared with TOVAL TOVALHIGH 2 DBG Debug Enable T...

Page 1362: ...ays has the value 0 15 8 CNTHIGH High byte of the Watchdog Counter CNTLOW Low byte of the Watchdog Counter 54 2 3 Watchdog Timeout Value Register WDOGx_TOVAL This section describes the watchdog timeou...

Page 1363: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOGx_WIN field descriptions Field Description 31 16 Reserved This field is reserved This read only field is reserved and always has the v...

Page 1364: ...fresh sequence until after the time value set in the WIN register See the following figure WDOG counter WIN Refresh opportunity in window mode TOVAL 0 Time Refresh opportunity not in window mode Figur...

Page 1365: ...re starting the refresh sequence disable the global interrupts Otherwise an interrupt could effectively invalidate the refresh sequence if the interrupt occurs before the refresh writes finish After t...

Page 1366: ...n you may want to reconfigure or disable the watchdog without forcing a reset first By setting CS UPDATE to 1 on the initial configuration of the watchdog after a reset you can reconfigure the watchdo...

Page 1367: ...clock source options selected by programming CS CLK bus clock internal Low Power Oscillator clock LPO_CLK This is the default source internal 8 MHz clock SIRC external clock SOSC The options allow so...

Page 1368: ...5 periods of the new clock source after the configuration time period 128 bus clocks ends This delay ensures a smooth transition before restarting the counter with the new configuration 54 3 4 Using i...

Page 1369: ...7 Fast testing of the watchdog Before executing application code in safety critical applications users are required to test that the watchdog works as expected and resets the MCU Testing every bit of...

Page 1370: ...d forces a reset 5 Confirm the WDOG flag in the system reset register is set indicating that the watchdog caused the reset The POR flag remains clear 6 Confirm that CS TST shows a test 10b or 11b was...

Page 1371: ...ted LLWU_P21 LLWU_P31 as reserved Updated section name and table title in section DMAMUX request sources In section ADC0 connections channel assignments for AD16 to AD22 Input signal SC1n DIFF 0 colum...

Page 1372: ...r changes No substantial content changes A 9 Security chapter changes No substantial content changes A 10 Debug chapter changes No substantial content changes A 11 Signal Multiplexing and Signal Descr...

Page 1373: ...changes No substantial content changes A 15 Kinetis ROM Bootloader changes No substantial content changes A 16 MMCAU changes No substantial content changes A 17 CMP changes No substantial content chan...

Page 1374: ...dule changes No substantial content changes A 22 EMVSIM changes No substantial content changes A 23 FlexIO changes No substantial content changes A 24 FMC changes No substantial content changes A 25 F...

Page 1375: ...bstantial content changes A 29 LPIT changes No substantial content changes A 30 LPSPI changes No substantial content changes A 31 LPTMR changes No substantial content changes A 32 LPUART changes No su...

Page 1376: ...al content changes A 37 PCC changes No substantial content changes A 38 PMC changes No substantial content changes A 39 Port Control and Interrupts PORT changes Moved the Overview section to be under...

Page 1377: ...content changes A 43 SCG changes No substantial content changes A 44 SIM changes No substantial content changes A 45 System Mode Controller changes SMC No substantial content changes A 46 TPM changes...

Page 1378: ...tent changes A 50 USB full speed OTG controller changes No substantial content changes Changed CLK_RECOVER_IRC_EN to reserved A 51 USB VREG changes No substantial content changes A 52 VREF_2V1 changes...

Page 1379: ...y for any vulnerability that is discovered Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP the NXP logo...

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