NXP Semiconductors K32 L2A Series, Reference Manual, Page: 534 / 1379

• Double buffered shifter operation for continuous data transfer
• Shifter concatenation to support large transfer sizes
• Automatic start/stop bit generation
• 1, 2, 4, 8, 16 or 32 multi-bit shift widths for parallel interface support
• Interrupt, DMA or polled transmit/receive operation
• Programmable baud rates independent of bus clock frequency, with support for
asynchronous operation during stop modes
• Highly flexible 16-bit timers with support for a variety of internal or external trigger,
reset, enable and disable conditions
• Programmable logic mode for integrating external digital logic functions on-chip or
combining pin/shifter/timer functions to generate complex outputs
• Programmable state machine for offloading basic system control functions from CPU
with support for up to 8 states, 8 outputs and 3 selectable inputs per state
22.1.3 Block Diagram
The following diagram gives a high-level overview of the configuration of FlexIO timers
and shifters.
31 0 SHIFTBUF0
SHIFTER0
31 0
SHIFTBUFi
SHIFTERi
FXIO_Dn
out/outen
FXIO_Dn
in
TIMER0 TIMERi
External Triggers
Input
Selection
Output
Selection
Timer
Selection
Figure 22-1. FlexIO block diagram
Introduction
K32 L2A Reference Manual, Rev. 2, 01/2020
534 NXP Semiconductors