NXP Semiconductors K32 L2A Series, Reference Manual, Page: 500 / 1379

EMVSIMx_RX_STATUS field descriptions (continued)
Field Description
Used to indicate when the calculated 16-bit CRC value matches the expected value for the current input
data stream. The value is calculated across all received characters from the point the CRC_EN bit is set in
the CTRL register. The current CRC residual can be reset by three mechanisms:
• Clear CRC_EN bit in CTRL register
• Set XMT_EN bit in ENABLE register
• Automatically by hardware when ETC flag is set at the end of a transmission.
0 Current CRC value does not match remainder.
1 Current calculated CRC value matches the expected result.
6
LRC_OK
LRC Check OK Flag
Used to indicate when the calculated 8-bit LRC value is correct for the current input data stream. The
value is calculated across all received characters from the point the LRC_EN bit is set in the CTRL
register. The current LRC residual can be reset by three mechanisms:
• Clear LRC_EN bit in CTRL register
• Set XMT_EN bit in ENABLE register
• Automatically by hardware when ETC flag is set at the end of a transmission.
0 Current LRC value does not match remainder.
1 Current calculated LRC value matches the expected result (i.e. zero).
5
RDTF
Receive Data Threshold Interrupt Flag
Interrupt flag asserted when total bytes in the Receive FIFO equal or is greater than the programmed
receive threshold RDT[3:0]. The RDTF flag will be set any time the number of unread bytes in the receive
FIFO is equal to or greater than the value set by RDT[3:0].
The flag can be cleared by reading enough bytes out of the receive FIFO so as to bring the number of
bytes left in the FIFO below the RDT[3:0] level. Another way to clear the flag is to set the RDT[3:0] level
higher than the number of unread bytes currently in the FIFO.
The RDTF flag will create an interrupt if the RDT_IM bit in the INT_MASK register is cleared.
0 Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default).
1 Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0].
4
RX_DATA
Receive Data Interrupt Flag
Interrupt asserted when a new data byte is received and entered into the Receive FIFO.
0 No new byte is received
1 New byte is received ans stored in Receive FIFO
3–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
RFO
Receive FIFO Overflow Flag
Used to indicate that the EMV SIM was unable to store received data due to already unread bytes in the
FIFO (FIFO full or almost full). It does not necessarily indicate that data has been lost. If the ONACK
control bit in the CNTL register is set, there will be a NACK pulse generated on bytes that would otherwise
cause a loss of data due to a full FIFO. These bytes should be retransmitted by the Smart Card which
implies that no data has actually been lost. In this case, the RFO flag is just an indicator that this situation
has occurred which may be helpful in system debug. For the case where ONACK is not set, a set RFO
flag does indicate a loss of data since all bytes received with the OEF flag set will indeed be lost (including
the byte that caused the bit to be set). The RFO flag will cause an interrupt if the RFO_IM bit in the
INT_MASK register. The RFO flag is a write-one-to-clear bit.
Table continues on the next page...
Memory Map and Registers
K32 L2A Reference Manual, Rev. 2, 01/2020
500 NXP Semiconductors