NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1124 / 1379

44.4.3 Run modes
The run modes supported by this device can be found here.
• Run (RUN)
• Very Low-Power Run (VLPR)
• High Speed Run (HSRUN)
44.4.3.1 RUN mode
This is the normal operating mode for the device.
This mode is selected after any reset. In order to reduce peak power consumption,
however, the SMC begins transitioning the device into VLPR mode during the reset
recovery sequence. When the Arm processor exits reset, it sets up the stack, program
counter (PC), and link register (LR):
• The processor reads the start SP (SP_main) from vector-table offset 0x000
• The processor reads the start PC from vector-table offset 0x004
• LR is set to 0xFFFF_FFFF.
To reduce power in this mode, disable the clocks to unused modules.
44.4.3.2 Very-Low Power Run (VLPR) mode
In VLPR mode, the on-chip voltage regulator is put into a stop mode regulation state. In
this state, the regulator is designed to supply enough current to the MCU over a reduced
frequency. To further reduce power in this mode, disable the clocks to unused modules
using their corresponding clock gating control bits in the PCC's registers.
Before entering this mode, the following conditions must be met:
• All clock monitors in the SCG must be disabled.
• The maximum frequencies of the system, bus, flash, and core are restricted. See the
Power Management details about which frequencies are supported.
• Mode protection must be set to allow VLP modes, that is, PMPROT[AVLP] is 1.
• PMCTRL[RUNM] must be set to 10b to enter VLPR.
• Flash programming/erasing is not allowed.
NOTE
Do not increase the clock frequency while in VLPR mode,
because the regulator is slow in responding and cannot manage
fast load transitions. In addition, do not modify the clock source
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
1124 NXP Semiconductors